Abstract: An apparatus for processing information includes first integrated circuit, a second integrated circuit and a bus coupling the first and second integrated circuits. The first integrated circuit includes functional logic. The second integrated circuit includes a clock synthesizer circuit. The clock synthesizer circuit provides clocks for the apparatus. The second integrated circuit includes I/O terminals for the clock synthesizer circuit and for the functional logic. The bus provides for serial transfer of information between the first and second integrated circuits. The information includes output signals from the functional logic provided to the I/O terminals and input signals for the functional logic from the I/O terminals.

Abstract: A radio selective paging receiver in which data can be shared between PC and the radio selective paging receiver and the system can be easily upgraded. An attribute setting means includes a card attribute and a shared memory space selective register. A self card shared memory space (memory means 1 and memory means 2) is selectively set based on a set value for a shared memory space selective register provided from the terminal. The control setting means executes selective process based on information stored in the register.

Abstract: A compact, high speed switch packaging arrangement or package provides reduced path lengths for electrical paths through the package. In particular, a printed circuit board switch backplane supports a switching subsystem and connects the switching subsystem to pairs of electrical connectors with the pairs of connectors being positioned on opposite edges of the same side of the backplane. A plurality of port boards for processing signals to be switched by the switching subsystem each include pairs of connectors which intermate with the pairs of connectors on the backplane. Port circuitry on the port boards is connected to the port board connectors to minimize trace lengths on the port boards by routing ports to the nearest one of the two connectors. The port boards are mounted to the backplane such that signals from the port boards are routed to the switching subsystem from two opposite sides of the switching subsystem.

Abstract: A method and apparatus for efficiently posting entries to a queue within the data processing system. Entries are posted by first processor with the entries being handled by second processor in the data processing system. The interrupt state associated with the queue is checked by the first processor. If the interrupt state is clear, then the entry is posted to the queue. This interrupt state is cleared only when all entries have been cleared from the queue by the second processor. In this manner, an efficient posting of entries to the queue may be accomplished.

Abstract: A communication interface circuit in an aircraft entertainment system uses a single Universal Asynchronous Receiver and Transmitter (UART) for sending and receiving data to and from a number of devices. The UART is coupled to a number of transceivers each having a transmitter buffer and a receiver buffer. A circuit is used to enable and disable the receiver buffers. A masking element is coupled between the receiver buffers and the UART to mask off the data from the disabled receiver buffers allow only the data from the enabled receiver buffer to go to the UART. With this communication interface circuit, the amount of hardware is significantly reduced.

Abstract: One aspect of the invention relates to a method for synchronizing control signals with scaled digital video data.