Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a second annealing process for activating the P-type impurity. By performing the above processes in that order, the N-type impurity ions in the N+ polysilicon gate electrode of the NMOSFET are sufficiently activated, thus preventing the problem of depletion. Also, fluctuation of a threshold voltage because of penetration of the P-type impurity ions in the gate electrode of the PMOSFET can be prevented in the PMOSFET.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of said transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic.

Abstract: A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Abstract: A method for making a semiconductor device is disclosed which comprises the step of applying a functional layer on a substrate, characterized in that said substrate is a laminate which comprises a support and a glass layer, said glass layer having a thickness of less than 700 &mgr;m. The support is preferably a plastic foil. The laminate has the combined benefits of low weight and high strength and is therefore a suitable substrate for making flat panel displays such as liquid crystal displays, plasma displays, field emission displays or organic light-emitting polymer displays. Preferred examples of the functional layer are e.g. electroconductive layers, liquid crystal orientation layers, color filters, electroluminescent layers, passivation layers and phosphor layers.

Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

Abstract: Trench capacitors are arranged in the form of a matrix at a constant pitch in row directions while being sequentially shifted between adjacent rows by a predetermined pitch. An element isolating insulator film is formed so as to surround active regions, each of which is adjacent to adjacent two capacitors in row directions, together with a partial region of the two capacitors. Transistors, which have gate electrodes continuously formed as word lines, are formed so as to be adjacent to the respective capacitors. One of the source and drain diffusion layers is connected to the capacitor node layer of a corresponding one of the capacitors via a connecting conductor. The other of the source and drain diffusion layers serves as a bit line contact layer shared by adjacent two transistors in the row directions, so that bit lines connected to the respective bit line contact layers in the row directions are formed. Three word lines are provided between adjacent bit line contact layers.

Abstract: A separating region and a method of forming a separating region of a semiconductor device is provided that increases reliability of the device by isolating respective gate electrodes. The separating region and method prevent voids from being formed within a trench of the separating region. The method of forming the separating region includes forming patterns of first insulating layers on a semiconductor substrate by selectively etching the first insulating layers to have at least one opening disposed in a defined region of the semiconductor substrate, forming side walls of a second insulating layer on both lateral sides of the patterns of the first insulating layers, and etching the side walls of the second insulating layer and the exposed semiconductor substrate using the patterns of the first insulating layers as a mask to form trenches in the semiconductor substrate. Since a selectively ratio of the sidewalls and the semiconductor substrate is preferably 1:1, the trenches have a prescribed shape and depth.