Abstract: An electronic device is provided. The electronic device includes a first housing including a first face and a second face, a second housing including a third face and a fourth face, a folding part rotatably connecting the first housing and the second housing, a flexible display disposed on the first face and the third face, a camera exposed through at least a portion of the fourth face, a memory configured to store instructions, and a processor configured to determine an orientation of the electronic device and a direction in which the camera is pointed while a camera application is executed, identify the first area or the second area as an area in which a preview image acquired through the camera is displayed based at least on the determined direction and the determined orientation, and display the preview image, acquired through the camera, in the identified area using the flexible display.

Abstract: A device for directing respired air includes a frame having a top portion, a bottom portion opposite the top portion, and at least one shoulder disposed between the top portion and the bottom portion to receive a portion of a headset. The device further includes an attachment mechanism coupled to the frame for releasably securing the frame to the headset. In addition, the device also includes a wall surface downwardly depending from the bottom portion of the frame to form a curved baffle. The curved baffle directs air corresponding to respiration toward the bottom portion of the frame, and thus toward an input interface of the headset when the frame is releasably secured to the headset.

Abstract: A display substrate and a manufacturing method, and a display device are provided. The display substrate includes a base substrate including a display region and a periphery region; and a shift register unit, a first power line and a second power line; an orthographic projection of the first power line on the base substrate is on a side of an orthographic projection of the shift register unit on the base substrate closer to the display region, an orthographic projection of the second power line on the base substrate is on a side of the orthographic projection of the shift register unit on the base substrate away from the display region, and the orthographic projection of the shift register unit on the base substrate is between the orthographic projection of the first power line on the base substrate and the orthographic projection of the second power line on the base substrate.

Abstract: The present disclosure provides a display panel, a method for driving the display panel and a display device. The display panel includes a display region and a non-display region. The non-display region includes a first bonding region, and further includes first connection lines connected to a plurality of gate lines respectively and second connection lines connected to a plurality of data lines respectively. The display panel further includes at least one chip on film, the chip on film includes a second bonding region, a first region, and a second region between the second bonding region and the first region. A scanning driving integrated circuitry connected to the second bonding region via first wirings and a data driving integrated circuitry connected to the second bonding region via second wirings are bonded in the first region. The first wirings and the second wirings are arranged at different layers in the second region.

Abstract: A shift register is provided, which may include a compensation selection circuit, a holding circuit, and N shift register circuits. The hold circuit may hold a blanking input signal. Each of the shift register circuits may include a blanking input circuit and an output circuit. The blanking input circuit may provide a blanking pull-down signal to a first node according to the blanking input signal and a blanking control signal. The output circuit may output a shift signal via a shift signal output terminal and output a first drive signal via a first drive signal output terminal according to a voltage of the first node. The compensation selection circuit may provide, according to a compensation selection control signal and the shift signal from one of the N shift register circuits, the blanking input signal to the holding circuit and the N shift register circuits.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.

Abstract: A gate driver on array (GOA) device and a display panel are proposed. In the present application, by adding a twenty-first transistor and a first control clock terminal electrically connected to the twenty-first transistor in a forward-reverse scan module to control potentials of a first node and a third node, a leakage of the first node during operation can be reduced, thereby improving reliability of the GOA device.

Abstract: Provided are a shift register, a display panel, a driving method, and a display device. The shift register includes a plurality of shift register units that are cascaded, where each of the plurality of shift register units includes a latch circuit, at least one scan switch circuit and at least one light emission control switch circuit; where the latch circuit is configured to, in response to a clock signal inputted by a clock signal input, latch an upper-stage shift signal inputted by an upper-stage shift signal input and output the upper-stage shift signal through a lower-stage shift signal output; each of the at least one scan switch circuit is configured to, in response to a lower-stage shift signal outputted by the lower-stage shift signal output, output a scan signal inputted by a scan signal input through a scan signal output.

Abstract: A shift register unit includes a signal input module, a first control module, a second control module, a signal output module and a total reset module. The total reset module is configured to control a potential of the pull-up node and a potential of the signal output terminal based on a potential of a first pull-down node, a potential of a second pull-down node and a level signal.

Abstract: A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.

Abstract: An address latch, a display device, and an address latching method are disclosed. The address latch includes a write control circuit, a write latch circuit, a latch control circuit, an intermediate latch circuit, and an output latch circuit. The write latch circuit is configured to latch an address data in response to N write control signals generated by the write control circuit, N data bits of the address data are divided into (M?1) data bit groups; the latch control circuit is configured to sequentially generate M latch control signals; the intermediate latch circuit is configured to, in response to first to (M?1)-th latch control signals, latch first to (M?1)-th data bit groups latched by the write latch circuit in a time-division manner; and the output latch circuit is configured to output the address data latched by the intermediate latch circuit in response to an M-th latch control signal.

Abstract: A display device including: first pixels connected to a first write line and a first compensation line; second pixels connected to a second write line and a second compensation line; third pixels connected to a third write line and a third compensation line; fourth pixels connected to a fourth write line and a fourth compensation line; fifth pixels connected to a fifth write line and a fifth compensation line; sixth pixels connected to a sixth write line and a sixth compensation line; seventh pixels connected to a seventh write line and a seventh compensation line; and eighth pixels connected to an eighth write line and an eighth compensation line, the first to fourth compensation lines are connected to a first node, the fifth and sixth compensation lines are connected to a second node, the seventh and eighth compensation lines are connected to a third node.

Abstract: A system and/or method that uses a body posture of a user to determine and modulate a content mode of a virtual reality system. The content mode may define the manner in which virtual reality content is presented to the user and/or the manner in which the user interacts with the virtual reality content. The user's body posture and/or a change in body posture may cause the content mode and/or the virtual reality content to change accordingly. In some implementations, primary content may be presented to the user according to a first content mode in response to the user sitting. Secondary virtual reality content may be presented to the user according to the second content mode in response to the user standing. As such, a user may initiate a change in the virtual reality content and/or the content mode by standing from a sitting posture and/or sitting from a standing posture.

Abstract: A driving method of display panel and a display device are provided, the driving method includes: taking a time duration of scanning at least two adjacent columns of pixel units as a driving period, a common electrodes of sub-pixels in the pixel units of a preset row are driven by different preset voltages in the current driving period, and the sub-pixels does not need to be driven by doubling the metal wiring and the driving device, thus to achieve the purpose of saving cost; and when the preset voltage is a positive or negative polarity driving voltage, the high voltage sub-pixel and the low-voltage sub-pixel in the pixel unit are driven by a preset driving mode.

Abstract: A scanning drive circuit, a driving method, a display panel, and a display apparatus are provided. The scanning drive circuit includes 1st to nth shift registers cascaded sequentially. Each shift register includes a pull-down unit, a pull-up unit, and first and second output units. The first output unit is electrically connected to a second supply voltage terminal and a first clock signal output terminal, and configured to output a level to a first output terminal based on levels of a second node and a third node. The second output unit is electrically connected to a third supply voltage terminal and a second clock signal output terminal, and configured to output a level to a second output terminal based on the levels of the second node and a fourth node. The first and the second output terminals of each shift register output effective levels sequentially.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: A shift register and a display device are provided. A first control device, a second control device and an output device of the shift register all receive a first power signal and a second power signal as working power signals. The first control device controls a signal of a first node and a signal of a second node in response to a first drive signal. The second control device controls the signal of the first node in response to a second drive signal. The output device outputs a third drive signal in response to the signal of the first node or the signal of the second node, and the third drive signal is generated and outputted by utilizing the first drive signal and the second drive signal, and simplifying a circuit configuration of the shift register for generating the third drive signal.

Abstract: A shift register circuit is provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a first control sub-circuit and a second control sub-circuit. The input sub-circuit is connected to a first signal input terminal, a second signal input terminal and a first node. The output sub-circuit is connected to the first node, a first clock signal terminal and a first output terminal. The first control sub-circuit is connected to a first power supply voltage terminal, a second power supply voltage terminal, the first node and a second node. The second control sub-circuit is connected to the second power supply voltage terminal, a third power supply voltage terminal, the second node and a third node, and the third node is further connected to the input sub-circuit.

Abstract: Provided is a display device having the following structure and driving method thereof. The display device comprises a circular display panel including an active area on which an image is displayed and a non-active area on which no image is displayed, a gate driving circuit disposed in the non-active area to drive a plurality of gate lines, a first data driving circuit disposed in the non-active area to drive first-group data lines in the circular display panel, and a second data driving circuit disposed in the non-active area, in a position opposite to the first data driving circuit with respect to the active area, to drive second-group data lines in the circular display panel. The frequency of a data clock is reduced using a plurality of data driving circuits in a pad area. The bezel size of a circular display panel is reduced.