Abstract: A voltage divider circuit comprises first and second transistor pairs 1 and 2 connected in series between a first standard voltage terminal VD and a second standard voltage terminal VS, and feedback control circuit 3. Each of transistor pairs comprises two NMOS transistors with the same electric characteristics, respectively. A divided ratio is set by a voltage applied to the gate terminals of these NMOS transistors M1-M4. Feedback-control circuit 3 comprises a load transistor pair 4 and an operational amplifier OP1. The circuit 3 performs feedback-control so that a voltage of connection lines L1 and L2 which connects first and second pairs of transistors becomes equal. Therefore, a high accurate divided voltage is outputted from between pairs 1 and 2 of transistors.