Abstract: A data processing system includes a number of subsystems all coupled in common to a system bus and communicate with each other by sending and receiving commands sent over the system bus. A central processing subsystem includes a response memory for storing indication of the responses sent by the receiving subsystem when receiving commands sent by the central processing subsystem. The responses include an acknowledge response, a not acknowledge response or no response--a timeout. Storing the acknowledge response and the timeout will enable the programmer to determine which of the three responses was received.

Abstract: A digital data processing system transfers information with an external device through an interconnect unit over a bus which includes separate sets of lines for transferring control information and transferring user information. The user information lines include bidirectional information transfer lines and undirectional antiparallel lines for transferring direction control signals and synchronization signals between the interconect unit and the external device, the direction control signals indentifying the direction of transfer over the information transfer lines, and the synchronization signals identifying when the transmitting unit has transmitted the signals and when the receiving unit has latched the signals. The control information lines include unidrectional antiparallel lines for transferring control information and a synchronization signal. The synchronization signal is transmitted when control information signals are being transmitted on the control information lines.

Abstract: This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions.