Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a ? doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration ? doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

Abstract: A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.

Abstract: A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.