Abstract: A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result. In the unchained mode, execution is accomplished by dispatching separate split-execution microinstructions to the first and second instruction execution units. In the chained mode, execution is accomplished by dispatching a single split-execution microinstruction to the first instruction execution unit and sending a chaining control signal or signal group to the second execution unit, causing it to execute its part of the fused arithmetic operation without needing an instruction.

Abstract: A true random number generation system includes a physical unclonable function (PUF) entropy device, a pseudo random number generator, and an encoding circuit. The PUF entropy device is used for generating a random number pool. The pseudo random number generator is used for generating a plurality of first number sequences. The encoding circuit is coupled to the PUF entropy device and the pseudo random number generator for generating a plurality of second number sequences according to the plurality of first number sequences and a plurality of third number sequences selected from the random number pool.

Abstract: A method for convolution in a convolutional neural network (CNN) is provided that includes accessing a coefficient value of a filter corresponding to an input feature map of a convolution layer of the CNN, and performing a block multiply accumulation operation on a block of data elements of the input feature map, the block of data elements corresponding to the coefficient value, wherein, for each data element of the block of data elements, a value of the data element is multiplied by the coefficient value and a result of the multiply is added to a corresponding data element in a corresponding output block of data elements comprised in an output feature map.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor acquires statistical information on a distribution of bits in floating point number data after executing an instruction on the floating point number data, and converts the floating point number data to fixed point number data.

Abstract: A secure computation system is provided. The system includes a distribution information generation apparatus that generates data distribution values, sign distribution values and carry distribution values from at least two fixed-point numbers by distributing each of the at least two fixed-point numbers using an additive secret sharing scheme; and a secure computation apparatus group including at least two secure computation apparatuses. The secure computation apparatus group includes: a secure digit extender; and a secure multiplier.

Abstract: Disclosed herein is a true random number generator (TRNG). The TRNG includes an enclosure defining a cavity and a cap covering the cavity and having a cap surface exposed to the cavity, the cap surface including radioactive nickel. An electronic sensor within a cavity detects electrons from the decay of the nickel and produces a signal for the detected energy. An amplifier is connected to the sensor and constructed to amplify the signal and feeds the signal to a filter. A processor connected to the filter generates a true random number based on the signal. This TRNG may be formed on an integrated circuit.

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction.

Abstract: Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Abstract: In a method for determining the modular inverse of a number, successive iterations are applied to two pairs each including a first variable and a second variable, such that at the end of each iteration and for each pair, the product of the second variable and of the number is equal to the first variable modulo a given module. Each iteration includes at least one division by two of the first variable of a first pair or of a second pair, or a combination of the first variable of the first pair and of the first variable of the second pair by addition or subtraction. At least some of the iterations including a combination by addition or subtraction include a step of storing the result of the combination in the first variable of a pair determined randomly from among the first pair and the second pair. An associated cryptographic processing device is also described.

Abstract: Performing processing using hardware counters in a computer system includes storing, in association with greatest common divisor (GCD) processing of the system, a first variable in a first redundant binary representation and a second variable in a second redundant binary representation. Each such redundant binary representation includes a respective sum term and a respective carry term, and a numerical value being represented by a redundant binary representation is equal to a sum of the sum and carry terms of the redundant binary representation. The process performs redundant arithmetic operations of the GCD processing on the first variable and second variables using hardware counter(s), of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form. The process uses output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.

Abstract: A non-transitory computer-readable recording medium stores therein an analysis program that causes a computer to execute a process including: dividing a Betti number sequence into a plurality of Betti number sequences, the Betti number sequence being included in a result of a persistent homology process performed on time series data, the plurality of Betti number sequences corresponding to different dimension of the Betti number sequence; and performing an analysis on each of the plurality of Betti number sequences.

Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Abstract: A device for generating a random electric signal, including an input duct, an output duct, a generator of magnetic particles generating magnetic particles in the input duct, a diffusion chamber connected to the input duct and the output duct, wherein the diffusion chamber is designed to diffuse the generated magnetic particles, a displacement unit for displacement of the generated magnetic particles towards the diffusion chamber, and a converter that is designed to generate an electrical signal proportional to a characteristic, wherein the characteristic is the particle density in the diffusion chamber or the passage of magnetic particles at a predetermined location of an output duct connected to the diffusion chamber.

Abstract: An arithmetic processing device includes a processor that calculates a constant multiplication value by multiplying a constant value obtained by dividing a first value by a natural logarithm of 2 and a data value, separates the constant multiplication value into an integer portion and a fractional portion, calculates a fractional power value corresponding to a value of the fractional portion, calculates an integer power value corresponding to a value obtained by multiplying a value of the integer portion by a second value, calculates a power addition value by adding the fractional power value and the integer power value, calculate a power subtraction value by subtracting the integer power value from the fractional power value, and calculate a division value by dividing the power subtraction value by the power addition value as a result of an execution of an arithmetic operation of a hyperbolic tangent function with the data value.

Abstract: Register restoration using recovery buffers. A restore request initiated by an application to restore one or more registers indicated by the restore request is obtained. The one or more registers are restored using a recovery buffer. The restoring scans the recovery buffer for the one or more registers indicated by the restore request, and restores the one or more registers using one or more values obtained from the recovery buffer.

Abstract: A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is connected at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.

Abstract: A computing system is described herein that expedites deep neural network (DNN) operations or other processing operations using a hardware accelerator. The hardware accelerator, in turn, includes a tensor-processing engine that works in conjunction with a scalar-processing unit (SPU). The tensor-processing engine handles various kinds of tensor-based operations required by the DNN, such as multiplying vectors by matrices, combining vectors with other vectors, transforming individual vectors, etc. The SPU performs scalar-based operations, such as forming the reciprocal of a scalar, generating the square root of a scalar, etc. According to one illustrative implementation, the computing system uses the same vector-based programmatic interface to interact with both the tensor-processing engine and the SPU.

Abstract: Techniques are disclosed relating to selection circuitry configured to select instruction operations to issue to one or more execution circuits of a processor. In some embodiments, an apparatus includes a plurality of execution circuits configured to perform one or more instruction operations. The apparatus may further include a plurality of instruction queues configured to store information indicative of the one or more instruction operations. In some embodiments, the apparatus may include a selection circuit configured to select a first plurality of instruction operations from a first instruction queue. The selection circuit may be configured to select a first instruction operation from the first plurality of instruction operations to issue to a first execution circuits.

Abstract: An apparatus comprising processing circuitry is provided, the processing circuitry comprising execution circuitry, commit circuitry, issue circuitry comprising an issue queue and selection circuitry, and a branch predictor. The processing circuitry is configured to identify a speculation barrier instruction in the commit queue. While an entry in the commit queue identifies a speculation barrier instruction, when a branch instruction that follows the speculation barrier instruction in the program order is selected for issue, the processing circuitry performs a first execution of the instruction, inhibiting updating of branch prediction data items associated with the branch instruction and inhibiting the selection circuitry from invalidating the associated issue queue entry.

Abstract: Snapshots are shared across save requests. A request to take a snapshot of one or more architected registers is obtained, and a determination is made as to whether the one or more architected registers have been modified since a previous snapshot that includes the one or more architected registers was taken. Based on determining the one or more architected registers have not been modified, the previous snapshot is used to satisfy the request to take the snapshot.