Abstract: A fiberoptic delay line architecture for generating multiple replicas of an input RF signal with variable replica-to-replica time resolution is provided in which the required hardware is kept to a minimum. A series of cascaded binary fiberoptic segment delay lines is used in which each cascaded binary fiberoptic segment delay line has an equal and defined number of segments but variable minimum time resolution. The minimum time resolution of each cascaded binary fiberoptic segment delay line increases by a multiple of two compared to the prior cascaded binary fiberoptic segment delay line. In this manner, the required number of segments and switches increases in a log.sub.2 .times.log.sub.2 relationship as the number of desired replicas and possible replica-to-replica delay values increases.
Type:
Grant
Filed:
May 8, 1992
Date of Patent:
March 1, 1994
Assignee:
Westinghouse Electric Corp.
Inventors:
Anastasios P. Goutzoulis, David K. Davies