Abstract: A method of calculating heat input to an alloying furnace which includes heat input means for use in the production of hot galvanized band steel comprising conveying a band steel of a selected steel variety through the alloying furnace and forming a plated deposition on the band steel in the alloying furnace comprising an alloyed layer of iron and zinc, establishing a formula defining a correlation between heat input and at least the steel variety, the plated deposition and the conveying speed of the band steel, inputting information which relates at least to the steel variety, the plated deposition, and the conveying speed, determining the heat input on the basis of the information inputted, and using the determined heat input to control the heat input means of the alloying furnace thereby controlling the formation of the iron and zinc alloyed layer plated deposition.
Abstract: The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.
Type:
Grant
Filed:
July 19, 1993
Date of Patent:
March 28, 1995
Assignee:
Texas Instruments, Incorporated
Inventors:
Michael F. Sullivan, Judith S. Hirsch, Stephanie W. Butler, Nicholas J. Tovell, Jerry A. Stefani, Purnendu K. Mozumder, Ulrich H. Wild, Chun-Jen J. Wang, Robert A. Hartzell
Abstract: An integrated circuit device ECL test access port (TAP) is constructed for low static current requirements and low power consumption when the TAP is inactive. The ECL test access port may conform with IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. An SCS logic circuit (50) is incorporated in the TAP controller coupled to the flip-flops (32,34,36,38) of the TAP controller n state finite machine for generating a current sink switch control signal (SCS) according to the state of the TAP controller. A current sink switch circuit (24) is coupled to respective current sinks of ECL gates incorporated in the boundary scan register (BSR/TDR1), design specific TAP data registers (DS/TDRs), TAP instruction register (TIR), and device identification register (DIR/TDR3). The current sink switch circuit (24) has an input coupled to the SCS logic circuit (50) to receive the current sink switch control signal (SCS).