Abstract: A terminal device for carrying out online processing with a host computer by using information stored in a memory includes a store control unit which receives the information and version information regarding the information from the host computer and stores, in the memory, the information with two copies of the version information attached at the beginning and the end of the information, respectively. The terminal device further includes a check unit which reads and compares the two copies of the version information stored in the memory, and an online processing unit which starts the online processing based on the information stored in the memory if the two copies of the version information are identical. In addition, the terminal device further includes a display unit which displays a message indicating an abnormality of the information if the two copies of the version information are contradictory (not identical).

Abstract: An intelligent status monitoring, reporting and control module is coupled to a SCSI bus that interconnects a cluster of SCSI-compatible data storage modules (e.g., magnetic disk drives). The status monitoring, reporting and control module is otherwise coupled to the cluster of SCSI-compatible data storage modules and to power maintenance and/or other maintenance subsystems of the cluster for monitoring and controlling states of the data storage modules and power maintenance and/or other maintenance subsystems that are not readily monitored or controlled directly by way of the SCSI bus. The status monitoring, reporting and control module sends status reports to a local or remote system supervisor and executes control commands supplied by the local or remote system supervisor. The status reports include reports about system temperature and power conditions. The executable commands include commands for regulating system temperature and power conditions.

Abstract: A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fetched, decoded, and macro-alias registers are restored with macro-alias data. To recover the state of the micro-alias registers, micro-alias data from a micro-operation of the flow may be loaded into the micro-alias register. Subsequently, control returns to the Micro-operation Sequence (MS) unit to issue further error correction Control micro-operations (Cuops). In order to simplify restart, the Cuops originating from the error-causing macroinstruction supplied by the translate programmable logic arrays (XLAT PLAs) are loaded into the Cuop registers, with their valid bits unasserted.

Abstract: There is provided a cross-connecting system capable of automatically detecting a connection error and a position where the connection error has occurred. The cross-connecting system has a cross-connecting apparatus which makes connection between a high-speed line and a low-speed line or between two high-speed lines so as to transfer a main signal therethrough. A line-connection information adding unit is provided for adding line-connection information to an overhead of the main signal. A line-connection information detecting unit is provided for detecting the line-connection information. A determining unit provides the line-connection information to the line-connection information adding unit, and determines a presence of a connection error along a line through which the main signal is transferred in accordance with the line-connection information received from a remote cross-connecting system.

Abstract: In an electronic mail associated type computer system network equipped with a computer system for executing a job and a general-purpose electronic mail system, a user of an electronic mail can freely recognize a condition of an execution result of a job performed in the computer system and a job execution result. Also, these results are available from a desired output device for the user. When a mail processing unit employed in the computer system analyzes a mail statement about the job execution derived from the electronic mail system, and the job execution is completed, this mail processing unit sends to the electronic mail system, such a mail statement for the completion of the job execution containing information about fail/safe execution result. Upon receipt of this report, the user designates the output device into a response mail so as to output the job execution result from the designated output device.

Abstract: A method for automated diagnosis of faults in a system containing repairable parts is performed by selecting a set of faults representing all known failures which can occur among the parts of the system, characterized by symptom data representing the expected passing or failing results for tests applied at selected test locations in the system, generating a fault/symptom matrix of the set of faults mapped to the expected passing and failing results for the selected test locations, then performing actual tests one or more test locations and correlating the actual passing or failing test results to the fault/symptom matrix in order to identify a suspect list of faults. Additional tests may be performed until the suspect list cannot be reduced further. For efficiency, the tests are selected according to which have most diagnostic significance. The design data for the parts of the system are captured and the fault/symptom matrix is preprocessed for diagnostic efficiency and speed during run time.

Abstract: A system for remote mirroring of digital data from a primary network server to a remote network server includes a primary data transfer unit and a remote data transfer unit which are connectable with one another by a conventional communication link. The primary data transfer unit sends mirrored data from the primary network server over the link to the remote data transfer unit which is located a safe distance away. Each data transfer unit includes a server interface and a link interface. The server interface is viewed by the network operating system as another disk drive controller. The link interface includes four interconnected parallel processors which perform read and write processes in parallel. The link interface also includes a channel service unit which may be tailored to commercial communications links such as T1, E1, or analog telephone lines connected by modems.

Abstract: In an arrangement of a mail terminal 1, an electronic mail system 2, a job control terminal 4, and a computer system 3, a user makes a proposal of a file operation via a mail by way of the mail terminal 1. The electronic mail system 2 stores therein the proposal mail, exchanges this proposal mail with the job control terminal 4, and furthermore distributes a file operation result to the respective mail terminals. The job control terminal 4 receives a mail from the electronic mail system 2, and interprets the proposal mail, thereby executing a conversion from a mail ID into a host ID, a judgement of an access authorization with respect to the designated file, and a production of an instruction to the computer process system 3. Furthermore, an execution host computer is selected by monitoring operation conditions of the host computers.

Abstract: A circuit controlling the transmission of information from a testing probe to an ICE.TM. base unit for debugging an electronic component having a dedicated bus. The circuit comprises a plurality of gate arrays coupled together to operate in a pipeline fashion. Each of the plurality of gate arrays includes a bus tracking component, a formatting component, filtering circuitry and address translation circuitry. The bus tracking component monitors the dedicated bus and transfers internal command signals to its associated formatting component and formatting components of the other gate arrays. The formatting component transfers only completed data to the ICE.TM. base unit for tracing. If in "Format" mode, the formatting component synchronously aligns the completed data and its associated addressing information before transferring such information to the ICE.TM. base unit. In "Raw" mode, however, information from the electronic component is immediately transferred to the ICE.TM. base unit without alignment.

Abstract: A method to and apparatus for communicating formatted data from mass storage media to a host computer is disclosed. In a preferred embodiment data is received through a serial digital signal processor (DSP) from an optical compact disk. The method and apparatus separates data bytes from auxiliary bytes, and stores them into separate and specific spaces within a DRAM. Error correction is performed after each block of data has been stored. After a given block has been verified, the system controller records the block number. The method and apparatus reduces the amount of address storage required to locate valid blocks of data in the DRAM. The method of the present invention increases the effective rate of transfer of data from the DRAM to a host computer.

Abstract: A physical image converting circuit is used in a memory tester for or an integrated circuit tester analyzing the failure of storage devices to be measured, in which data are read as logical images from each of the corresponding storage regions to each input/output bit and are stored in each of the corresponding storage regions to each input/output bit of a failure analysis memory used for failure analysis. The physical image converting circuit converts the logical image of the readout data from the failure analysis memory into physical images so that the readout data corresponds to a physical position on a wafer chip of the failure analysis memory. The physical image converting circuit includes a counter, an address converting circuit, a failure analysis memory, and a selector. The counter generates increment addresses corresponding to at least a storage capacity of failure analysis memory.

Abstract: A method and system for enabling the monitoring of a target software routine in a stripped object executable on a computer system. The system enables monitor instrumentation of the target routine without access to or recompiling the source code of the object and without access to information required to link with the stripped object. A single demultiplexor entry for each target routine provides access to common instrumentation code and to user specified entry and exit routines for the particular target routine. Common instrumentation code is not replicated when used to monitor a number of software programs. User specified entry and exit routines are used to collect selected performance and system state data. Common instrumentation code is provided to link the target routines to the user specified entry and exit routines. The standard link interface allows the entry and exit routines to be written in high level languages.

Abstract: A method and apparatus for the analysis of a computer process is disclosed. The method consists of the steps of analyzing a target process and constructing a model and repository which are representative of the control and non-control components contained within the original target process respectively. The resultant model and repository are executed, and their execution is representative of the original target process. Structures created during the execution of the model and repository assist a user to identify failures which occur during the execution, and then locate the fault(s) responsible for the failures as well as places within the target process where modifications due to new requirements are needed. An alternative form of object code is proposed which consists of two components, control and non-control components.

Abstract: A buffer memory holding blocks of data received from a main host computer has dedicated portions for data destined for different sets of sender-receiver units. Each sender-receiver unit has a channel bus path to the buffer memory and each channel bus is monitored by an on-the-fly integrity checking circuit.A control processor and associated bus arbitration logic provide signals to a multiplexer so as to allocate equal access periods to each channel bus for connection to the buffer memory. A data feeder control on each transfer channel senses the availability of data block words in each dedicated segment of the buffer memory so that partial transfers of word blocks may occur on minor cycles with subsequent completion of the blocks of data words on a major transfer cycle.

Abstract: A parity generation circuit for an internal cache memory of a computer processor. The parity generation circuit generates parity for both reading and writing during execution of a single processor instruction. The parity generation circuit saves processor circuitry by sharing one parity logic tree for both reading and writing. During one clock phase, a multiplexer routes data to the memory through the parity logic tree and a demultiplexer routes parity from the parity logic tree to the memory. During a second clock phase, the multiplexer routes data from the memory through the parity logic tree and the demultiplexer routes parity from the parity logic tree to the processor.

Abstract: A method and system for rebuilding storage structures located within one or more structure processing facilities of a data processing system. A connection is made to a first storage structure having a name and one or more predefined characteristics. Thereafter, a second storage structure is allocated having the same name as the first structure, however, one or more of the predefined characteristics of the second structure are different than the predefined characteristics of the first structure. The second structure may be used for planned system reconfigurations or for recovery from system failures. During the rebuilding process, notification of phases of the rebuilding process are given to the active users. Further, a capability is provided for terminating the rebuilding process. In addition, a method and system for coordinating phases of user defined processing is provided.

Abstract: A data backup system implements coordination between a Database Server and a Backup Server to produce a recoverable database dump. By utilizing a technique referred to as stripe affinity, a mechanism is disclosed for ensuring the integrity of a database backup made to multiple archive devices simultaneously. In addition, by utilizing stripe affinity, archived data may be reloaded from fewer archive devices than were used to make the original backup. A task scheduler mechanism allocates processor time among the tasks that comprise the backup system. In this way the I/O service tasks can process their event queues while the current set of allocation pages are also being processed.

Abstract: A system for searching for alternative routes in a network at the time of a failure in a node or link which executes a stage for initiation of failure restoration processing which starts up failure restoration processing in accordance with various types of messages when a failure occurs at a link or node, a stage for processing a restoration message for searching for an alternative route, a stage for processing an acknowledgment message for reserving an alternative route, a stage for processing a cancellation message for cancelling reservation of an alternative route, a stage for processing a confirmation message for confirming a reserved alternative route and making a switching of cross-connect equipment, a stage for processing a cross-connection completion message for notifying the completion of switching of the cross-connect equipment to the nodes, a stage for processing a cross-connection acknowledgment message for confirming the completion of switching of all of the cross-connect equipment on the alterna

Abstract: A fault tolerant change distribution method in a distributed database system including at least two separate intercommunicating databases. At least part of the stored data is identical in the different databases. The changeable data items of the databases are provided with state fields, whereby, after a data item has been added, deleted or modified, the state field of the respective data item is set in a state which indicates that the change should be transmitted to another database. When the change has been transmitted to the other database, an acknowledgement of receipt of the change is awaited from the other database, whereafter the state field of the data item is set in a state which indicates that the change has been transmitted.

Abstract: Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system.