Abstract: A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Abstract: A garbage collector can initialize a garbage collection cycle. The cycle can include a mark phase and a sweep phase. The mark phase can traverses a complete set of objects in a heap. The heap can be associated with a virtual application memory including a primary memory and a secondary memory. The virtual application memory can be managed by a virtual memory manager, which moves pages between the primary memory and the secondary memory. Information can be bidirectionally communicated between a garbage collector and the virtual memory manager. A default order in which the objects are evaluated during the mark phase can be altered to minimize paging activity. The altering of the order can be based at least in part upon information obtained from the virtual memory manager.

Abstract: In one embodiment, a virtual NUMA system may be formed from multiple computer systems coupled to a network such as InfiniBand, Ethernet, etc. Each computer includes one or more software modules which present the resources of the computers as a virtual NUMA machine. A single instance of a guest operating system executes on the virtual NUMA machine. The guest operating system is designed to execute on a NUMA system and executes without modification on the virtual machine. The memory model of the virtual NUMA machine includes a single writer, multiple reader memory model.

Abstract: A management computer comprises: a cascade configuration storage section which stores volume cascade configuration information which is information related to the configuration of the volume cascade; an expansion target volume determination section which determines any logical volume of the plurality of logical volumes as a target of expansion; a cascade configuration specifying section which specifies, from the volume cascade configuration information, other logical volume of the volume cascade to which the expansion target logical volume belongs; and a capacity expansion control section which transmits, to the storage system group, a capacity expansion instruction which designates two or more target volumes and the capacity obtained after expanding each of the two or more target volumes, the two or more target volumes constituting a target volume cascade comprising the expansion target logical volume and the specified other logical volume.

Abstract: A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.

Abstract: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table having a plurality of entries, each entry comprising an address, a value, and a link. The embodiments may include determining whether there is a collision of the value with a value stored in the entry; inserting the value in the entry if there is no collision; and generating the addresses of further entries until an entry is found in which the value can be inserted if there is a collision. The embodiments may include generating a plurality of addresses of entries based upon the address of a previously generated entry.

Abstract: A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of the pages. A processor blade is provided that includes a first memory area to store at least one of the pages and a second memory area configured to store an address of each of the pages and a hint value that is assigned to each of the pages. An address of each of the pages is stored in the second memory area, and a hint is assigned to each of the pages, where the hint is one of: likely to be accessed, may be accessed, and unlikely to be accessed. The page is then stored in storage blade cache memory based on the hint.

Abstract: A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.

Abstract: A method of re-mapping a flash memory, which minimizes the number of times the flash memory, is accessed and helps to evenly use the entire area of the flash memory, is provided. The method includes arranging a plurality of physical units yet to be mapped according to their erase count values, and sequentially mapping the physical units to a logic unit in such a manner that a physical unit having a smaller erase count value is mapped to the logic unit ahead of a physical unit having a larger erase count value.

Abstract: To reduce a burden imposed on a system administrator in restore operation, there is provided a computer system including at least one storage system, at least one host computer, and a management computer, in which: the storage system includes: a first processor; a first memory; and a disk drive; the host computer includes: a second processor; and a second memory; the management computer includes: a third processor; and a third memory; the second processor executes plurality of applications; the first processor and the second processor create check points to be used to maintain consistency of data at predetermined timing for the respective applications; and a third processor obtains recovery conditions, which are conditions for a check point to be used for a recovery, and identifies a check point, which satisfies the obtained conditions, from the created check points for the respective applications.

Abstract: A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.

Abstract: Systems and methods for improving the performance of a multiprocessor system by enabling a first processor to initiate the retrieval of data and the storage of the data in the cache memory of a second processor. One embodiment comprises a system having a plurality of processors coupled to a bus, where each processor has a corresponding cache memory. The processors are configured so that a first one of the processors can issue a preload command directing a target processor to load data into the target processor's cache memory. The preload command may be issued in response to a preload instruction in program code, or in response to an event. The first processor may include an explicit identifier of the target processor in the preload command, or the selection of the target processor may be left to another agent, such as an arbitrator coupled to the bus.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Abstract: A file system migrates a traditional volume to a virtual volume without data copying. In an embodiment, a traditional volume index node is selected for migration. The traditional volume index node is converted to a virtual volume index node. In one embodiment, the virtual volume index node provides both physical address information and virtual address information.

Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Abstract: A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.

Abstract: One embodiment of the present invention provides a system that facilitates concurrent non-transactional operations in a transactional memory system. During operation, the system receives a load instruction related to a local transaction. Next, the system determines if an entry for the memory location requested by the load instruction already exists in the transaction buffer. If not, the system allocates an entry for the memory location in the transaction buffer, reads data for the load instruction from the cache, and stores the data in the transaction buffer. Finally, the system returns the data to the processor to complete the load instruction. In this way, if a remote non-transactional store instruction is received during the transaction, the remote non-transactional store proceeds and does not cause the local transaction to abort.

Abstract: The invention provides a method, system and computer program product for caching dynamic portal pages without changing the existing caching proxy infrastructure or the transportation protocol used by providing an advanced caching component. An advanced caching component provides the functionality that additional dynamic page specific cache information is provided as part of the response including the portal page. Each component in the portal that dynamically contributes page fragments to be aggregated to a portal page provides dynamic component specific cache information which includes component specific cache scope and expiration values. The component specific cache scope and cache expiration values are used to calculate dynamic page specific cache information resulting in a common minimum cache scope and a common minimum cache expiration values for a portal page to be aggregated.

Abstract: A method and a device for converting a virtual address of a program executed by a processor and provided by a program counter into a physical address in a program memory, the program having been stored in the memory in at least one segment of consecutive addresses. The method includes adding to each address provided by the program counter a number corresponding to the offset between the memory address and the virtual address provided by the program counter, and detecting a possible overflow from the current segment by comparing the obtained physical address with the start and end addresses of the considered segment.

Abstract: A controller comprises a host interface section and a processing circuit. The host interface section receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory. The processing circuit processes the command sequence outputted from the host apparatus to the first nonvolatile semiconductor memory, and controls writing, reading and erase of data to a second nonvolatile semiconductor memory, according to the command sequence.