Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for automated data modification reconstruction and attribution. One of the methods includes determining two or more net modifications between a first backup and a second backup; attributing, for each of the two or more net modifications, the net modification to an entity from a plurality of entities; determining, for an event of interest and using first data that indicates the net modifications, a likelihood that a modification during the event of interest is attributable to a first entity; determining whether the likelihood satisfies a likelihood criterion; and performing, in response to determining that the likelihood satisfies the likelihood criterion, an action for the event of interest using second information for the first entity and the modification.

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with actually controlling a memory cell array of flash memory device generating failure errors.

Abstract: The disclosure discloses a storage controller, a memory management method, and a storage device, the memory management method including: identifying a current power mode of a host system; obtaining a target command from a command queue; in response to determining that the target command is used to enable a write booster mode, determining whether the power mode is a highest level; in response to determining that the power mode is the highest level, determining whether a cache block currently in use is a physical block of a triple-level cell type; in response to determining that the cache block currently in use belongs to the triple-level cell type, freezing the cache block of the triple-level cell type; using a physical block of a single-level cell type as a new cache block to write cache data; and enabling the write booster mode, and sending an enabling completed response.

Abstract: A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system.

Abstract: A method includes receiving, at a computing device, inventory data identifying a plurality of computer readable storage devices. The method further includes receiving, at the computing device, a first request to perform a memory management operation. The method further includes sending, from the computing device to a first station, a command to perform the memory management operation on a first portion of the plurality of computer readable storage devices connected to the first station. The method further includes receiving, at the computing device from the first station, first results data indicating results of the memory management operation at the first station. The method further includes updating the inventory data based on the first results data.

Abstract: A computing system can include memory management capabilities. In one embodiment, the system receives a request to allocate a portion of memory, where the request to allocate the portion of memory comprises a memory pool instance; determines a memory pool subinstance from which to allocate the portion of memory based on the memory pool instance; and obtains the portion of memory from the determined memory pool subinstance.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Abstract: A method of compressing data for transfer between a local storage of a processor and an external storage. The data is formed in an array of three or more dimensions and the method comprises sequentially reading data stored in the local storage to a compressor in units of data. Each unit has a predetermined unit size corresponding to an integer number of a tile size. At an extremity of the array, a partial unit of data is read in a case that the array size is not an integer multiple of the unit size. The partial unit of data is filled at the compressor and the filled data is compressed on a tile-by-tile basis to form compressed data. The compressed data associated with the unit of data is transferred to the external storage.

Abstract: A data storage device receives a speculative read command from a host identifying logical block addresses. The speculative read command is not required be to executed within a certain amount of time or even at all. The data storage device at least partially executes the speculative read command in response to determining that such execution will not reduce performance of the data storage device. At least partially executing the speculative read command causes data associated with at least some of the logical block addresses to be read from the non-volatile memory and stored in at least one buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

Abstract: Techniques are provided for implementing a garbage collection process and a prediction read ahead mechanism to prefetch keys into memory to improve the efficiency and speed of the garbage collection process. A log structured merge tree is used to store keys of key-value pairs within a key-value store. If a key is no longer referenced by any worker nodes of a distributed storage architecture, then the key can be freed to store other data. Accordingly, garbage collection is performed to identify and free unused keys. The speed and efficiency of garbage collection is improved by dynamically adjusting the amount and rate at which keys are prefetched from disk and cached into faster memory for processing by the garbage collection process.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Abstract: A data storage system stores a plurality of partitions for a volume and at least one parity partition for the volume. The parity partition includes erasure encoded data that enables any one of the partitions to be reconstructed using the erasure encoded data of the parity partition. Additionally, the data storage system is configured to generate parity data updates in response to modifications to the volume and store updated parity data in the parity partition, such that a current state of any of the partitions of the volume can be re-created in response to a loss of one of the partitions.

Abstract: Disclosed embodiments relate to one or more techniques to control access by a requestor of a computing system to a shared memory resource. In one embodiment, a technique includes determining a number (N) of pending requests to be sent to the memory by the requestor, determining a number (M) of requests that the requestor is limited to sending based on an amount of buffering resources available, and comparing M to N. When N is both greater than zero and less than or equal to M, the requestor sends the N pending requests to the memory. When N is both greater than zero and greater than M, M is compared to a hysteresis value (R) and, when M is less than R, the requestor sends R of the N pending requests to the memory.

Abstract: A method for updates in a storage system is provided. The method includes writing identifiers, associated with data to be stored, to storage units of the storage system and writing trim records indicative of identifiers that are allowed to not exist in the storage system to the storage units. The method includes determining whether stored data corresponding to records of identifiers is valid based on the records of the identifiers and the trim records.

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During a burn-in operation of the memory sub-system in a manufacturing facility, the memory sub-system is configured to perform read/write operations for the generation of a proof of space plot. After the burn-in operation, the memory sub-system is provided as a product of the manufacturing facility; and the proof of space plot stored in the memory sub-system is provided as a by-product of the burn-in operation.

Abstract: Systems and methods for replicating data from storage. Snapshots are taken of the volumes in physical storage. The snapshot volumes are exposed to a virtual replication system. Using the snapshots, differential or changed data can be identified. The identified data is then replicated by the virtual replication system to a remove virtual replication system.

Abstract: A method for oversubscribing a host memory of a host running a virtual machine monitor (VMM), comprising, examining a virtual machine (VM) memory for a VM for metadata associated with the VM memory, the metadata maintained by a guest OS running on the VM, collecting the metadata for the VM memory, and managing the VM memory using the metadata for oversubscribing a host memory.

Abstract: Recording a trace of code execution using reference bits in a processor cache. A computing device comprises processing units and a shared cache. The shared cache includes a plurality of cache lines that is each associated with a plurality of accounting bits, which each includes a reference bits portion. Stored control logic uses these reference bits to log a second read operation by a second processing unit in reference to an already logged first read operation by a first processing unit.

Abstract: A memory controller having an improved operating speed controls a memory device in response to a request from a host. The memory controller includes: a processor for driving firmware for controlling communication between the host and the memory device; a map data receiver for receiving map data including a plurality of mapping entries including physical block addresses, for operations to be performed on the memory device from the memory device under the control of the processor; and a map data controller for checking a mapping entry corresponding to the request, which are received from the map data receiver, snooping the detected mapping entry and outputting the detected mapping entry to the processor.