Patents Examined by Alan Tran
  • Patent number: 5491643
    Abstract: A method suitable for optimizing parameters characteristic of a preselected portion of an object developed in a rapid prototyping system. The method comprises the steps of identifying an object characteristic space comprising at least one dimension, the or each dimension defining a continuum for one object parameter; and, selecting a predetermined subset of said object characteristic space comprising desired optimal characteristics of the preselected portion of the object.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: February 13, 1996
    Assignee: Stratasys, Inc.
    Inventor: John S. Batchelder
  • Patent number: 5485401
    Abstract: The present invention resides in a probe excitation and testing ("PET") system that can apply either a normal excitation or a "small" bias test excitation to overfill protection probes mounted within storage and transport tanks used to store, e.g., flammable fluids. The PET system applies the normal excitation for normal operation of the probes to provide overfill protection, and applies a "small" bias test excitation to the probes for performing diagnostic tests, including anti-cheating. The PET system can also perform a probe signature validation test under normal excitation to ascertain whether the probes are responding thereto in accordance with specifications relating to characteristic parameters of the probes' output waveforms, e.g., duty cycle, magnitude, and period.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: January 16, 1996
    Assignee: Scully Signal Company
    Inventor: Gary R. Cadman
  • Patent number: 5459736
    Abstract: A scan path circuit for testing multi-phase clocks of sequential circuits is capable of preventing a clock skewing and includes a plurality of scan circuits coupled to respective clock testing circuits each including a latch circuit receiving a clock signal and a clock mode signal to output a latch output signal, and a control gate which outputs a control signal. The scan circuits each includes two latch circuits and a control gate which receives a test clock signal. The scan circuits operate as flip-flops during a non-testing period. When a scan mode signal is "0" and a clock signal is "1" an output of the latch circuit of the testing circuit becomes "1" and an output of the control gate thereof becomes a value of a first test clock signal. This value is used as a clock of the scan circuit, and a data input signal is taken into the respective scan circuit.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: October 17, 1995
    Assignee: NEC Corporation
    Inventor: Yoshiyuki Nakamura
  • Patent number: 5453993
    Abstract: Disclosed is a semiconductor integrated circuit which can be tested with a high-speed clock of actual operation level or more, even if a relatively low-priced IC tester which is not capable of supplying high-speed clocks is employed, and a method of testing the same. An exclusive OR gate (2) of the semiconductor integrated circuit receives the first test clock (TCLK1) through the first test clock input pin (P1) into the first input and the second test clock (TCLK2) through the second test clock input pin (P2) into the second input, to output a high-speed clock (SCLK) resulting from the test clocks to an A input of a selector (3). Thus, the semiconductor interacted circuit internally generates the high-speed clock having higher frequency than that of the test clock to operate an internal circuit, thereby being tested with clock frequency of actual operation level or more even by means of the relatively low-priced IC tester.
    Type: Grant
    Filed: January 25, 1994
    Date of Patent: September 26, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Kitaguchi, Masaharu Taniguchi
  • Patent number: 5452238
    Abstract: A method, useful in computer-aided design, for finding possible configurations of a system having a collection of geometric entities and constraints. The method represents the geometric entities in terms of degrees of freedom and systematically satisfies the constraints reducing the degrees of freedom of the geometric entities. The method uses a number of specialized routines, called plan fragments, which satisfy a particular constraint relating to a particular geometric entity. Each plan fragment changes the configuration of a geometric entity in space--i.e. the location and orientation--satisfying a constraint and reducing a degree of freedom. The series of plan fragments which reduce the degrees of freedom and satisfy the constraints comprise an assembly plan for possible configurations of the system. The method identifies overconstrained, fully constrained, and underconstrained systems to the user and assists in finding possible configurations if the constraints are changed, added, or deleted.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: September 19, 1995
    Assignee: Schlumberger Technology Corporation
    Inventors: Glenn A. Kramer, Walid T. Keyrouz, Jahir A. Pabon
  • Patent number: 5450414
    Abstract: The testability of a near-acyclic circuit (14) can be enhanced by the addition of one or more control points (36) and observation points (34) to allow for increased observability and controllability of selected nodes (28). The control points (36) and/or test points (34) are added by first computing the controllability, observability and fault detection probability at each node. A fault is then selected. If either the controllability or observability for such fault is not inside a prescribed value range, and the fault detection probability is below a prescribed value, then either a control point (36) and/or a observation point (34) may be added.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: September 12, 1995
    Assignee: AT&T Corp.
    Inventor: Chih-Jen Lin
  • Patent number: 5450415
    Abstract: The invention discloses a boundary scan cell circuit for use in checking a wire, establishing a connection between the output pin of one IC and the input pin of the other IC, for stuck-at "0"/"1" faults. In an input boundary scan cell circuit in connection with the input pin, a third selector, in response to a control signal, selects one of a signal from a logic signal input terminal and an XOR from an arithmetic unit thereby outputting a signal thus selected. The output of the third selector is latched by a first flip-flop. The arithmetic unit performs the XOR addition of the output of the first flip-flop and the value of a logic signal from the logic signal input terminal. The result of the XOR addition is scanned-out at a scan signal output terminal. This reduces the number of shift operation cycles required for scan-out of the test result thereby shortening the time taken for testing.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: September 12, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takehiro Kamada
  • Patent number: 5442643
    Abstract: An integrated circuit (IC) chip which can be tested even after being packaged on a circuit board together with other IC chips, and a method of testing such IC chips on the circuit board are provided. The IC chip has a main IC section to which a particular function is assigned, and a plurality of testing circuits capable of freely extracting output data of the main IC section on a common bus. An interface is also provided on the IC chip which receives signals for controlling the testing circuits from the outside. The testing circuits, therefore, can selectively hold data sent from the outside or data from the main IC section and then send the data out via input/output terminals thereof or the interface.
    Type: Grant
    Filed: March 23, 1993
    Date of Patent: August 15, 1995
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Kaoru Adachi
  • Patent number: 5442555
    Abstract: A two-level hierarchical approach for process fault diagnosis is an operating system employs a function-oriented approach at a first level and a component characteristic-oriented approach at a second level, where the decision-making procedure is structured in order of decreasing intelligence with increasing precision. At the first level, the diagnostic method is general and has knowledge of the overall process including a wide variety of plant transients and the functional behavior of the process components. An expert system classifies malfunctions by function to narrow the diagnostic focus to a particular set of possible faulty components that could be responsible for the detected functional misbehavior of the operating system. At the second level, the diagnostic method limits its scope to component malfunctions, using more detailed knowledge of component characteristics.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: August 15, 1995
    Assignee: Argonne National Laboratory
    Inventors: Jaques Reifman, Thomas Y. C. Wei
  • Patent number: 5430660
    Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: July 4, 1995
    Assignee: Tektronix, Inc.
    Inventors: Jonathan Lueker, John Hengeveld, Brad Needham, Burt Price, Jim Schlegel, Mehrab Sedeh
  • Patent number: 5428626
    Abstract: A timing analyzer for embedded testing of printed circuit boards, integrated circuits or multi-chip modules is in the form of an integrated circuit that may be included as part of the printed circuit board, integrated circuit or multi-chip module being tested. Each channel of a data path to be tested has a timing analyzer circuit that may be coupled into the path when enabled for testing. The timing analyzer circuit has instruction memories that are loaded with time event commands via a suitable program bus, such as a boundary scan interface. Each event command has a clock portion, an interpolation portion and a drive output portion. A counter counts down the clock portion using a system clock from the board/circuit/module to produce a terminate pulse. The terminate pulse is delayed by an increment less than one period of the system clock by a delay interpolator, the amount of delay being determined by the interpolation portion, to generate a trigger signal.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: June 27, 1995
    Assignee: Tektronix, Inc.
    Inventors: Arnold M. Frisch, Thomas A. Almy
  • Patent number: 5428624
    Abstract: A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: June 27, 1995
    Assignee: Storage Technology Corporation
    Inventors: Larry D. Blair, John C. Joy, William H. Dittenhofer
  • Patent number: 5428549
    Abstract: A fault location system comprises current and voltage transducers 10, filters 12, and a multiplexor 14, the latter outputting an interleaved stream of analog phase current and voltage signal samples, as well as neutral current samples. The analog multiplex output by the multiplexor 14 is digitized by an analog-to-digital converter 16. The output of the analog-to-digital converter 16 is fed to a digital signal processing block 18. The multiplexor necessarily introduces a time-skew between the successive samples for each channel and also introduces a time-skew between the respective channels. The system corrects the sample-to-sample time-skew for each channel, and then derives current and voltage phasors from the time-skew corrected data. Thereafter, the phasors are adjusted to correct for channel-to-channel phase-skew. In this manner, the digital signal processing block produces phasor data for each of the sampled channels. The phasor data is stored in a memory 20.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 27, 1995
    Assignee: ABB Power T&D Company
    Inventor: Muchuan M. Chen
  • Patent number: 5428560
    Abstract: A simulator, in particular for simulating thermal batteries, the simulator delivering an output voltage U.sub.bat across output terminals thereof, said output voltage being a function of a current I.sub.out delivered, into a load connected to said terminals, and of an e.m.f. parameter. E.sub.g and of an internal resistance parameter R.sub.g that are determined from simulation profiles that give successive values taken by said parameters under real battery operating conditions during an active life cycle of a given battery. The simulator includes computer equipment delivering the simulation profiles in the form of e.m.f. references C.sub.Eg and internal resistance references C.sub.Rg to a battery simulation card which, in order to generate the output voltage U.sub.bat of the simulator at the output of said voltage programmable power supply feeds said power supply with a battery voltage reference C.sub.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: June 27, 1995
    Assignee: Aerospatiale Societe Nationale Industrielle
    Inventors: Serge Leon, Patrick Grain, Serge Bard
  • Patent number: 5428555
    Abstract: An interactive computer controlled management system for real-time data gathering and analysis of process information relating to a plurality of data sources in a facility and for controlling process functions of the data sources. In a preferred embodiment, the data sources include gas cabinet panels and related process equipment typically found in a wafer fab facility. The system operates in a distributed processor environment and includes a host processor having graphic, control and user interfaces and a multi-ported processor networked to the host processor. The multi-ported process includes protocol sensitive hardware interfaces for communication with the programmable logic controllers of each particular data source. The multi-ported processor also includes software means for emulating a common protocol such that each gas cabinet or other connected device appears to the host processor as an address location in a memory of the multi-ported processor.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: June 27, 1995
    Assignee: Praxair, Inc.
    Inventors: Sean C. Starkey, Richard Penstein
  • Patent number: 5426589
    Abstract: Disclosed herein is a method of and an apparatus for limiting electrical loads due to electrical equipment on an electric vehicle. In the electrical load limiting apparatus, a desired running distance is inputted by a desired running distance inputting device and a depth of discharge of a battery is detected by a battery condition detecting device. Ambient environment data for the electric vehicle are obtained from an illuminance sensor, a temperature sensor and a raindrop sensor. An arithmetic device is activated to determine and compute running conditions on the basis of the desired running distance, the depth of discharge and the ambient environment data. The electrical loads are controlled by an electrical load limiting device based on the result of the determination by the arithmetic device.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: June 20, 1995
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Masashi Kitagawa, Kenichiro Kimura
  • Patent number: 5424958
    Abstract: The method allocates a demanded amount of power to a plurality of power output apparatus, each power apparatus having characteristic curves associated therewith, and the total power outputted from the plurality of power apparatus results in a minimum cost for generating the power. Each boiler is allocated a quantity of waste fuel to be used in the generation of power, the quantity of waste fuel to be a predetermined total over a predetermined time period. Data is entered for each of the power apparatus into a controller. Optimal solutions are generated for all valid possible output power demands using an optimization by parts technique within bounds of each power apparatus. The solutions indicate the portion of power each power apparatus is to supply to provide the total power demanded at minimal cost. The solutions are stored in tables within a storage unit of the controller.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: June 13, 1995
    Assignee: Honeywell Inc
    Inventor: Stephen L. Knupp
  • Patent number: 5418735
    Abstract: Event packets are input to an event handler both in a scheduling phase and in a dispatching phase of an event scheduler. In the scheduling phase, EVCNT of a device of an occurring event is counted up by 1, and in the dispatching phase, EVCNT of a device of a mature event is counted down. In the dispatching phase multiple events are detected based on the EVCNT. If an old status of the top event of the multiple events is equal to a current status of the device, it is decided that event-outstripping has occurred, and events are cancelled. If the old status is not equal to the current status, it is decided that a glitch occurs, and events are modified according to a given mode value. Since the event handler can be implemented by a simple combination logic unit, acceleration performance of a logic simulation accelerator is not adversely affected.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: May 23, 1995
    Assignee: Fujitsiu Limited
    Inventor: Minoru Saitoh
  • Patent number: 5414641
    Abstract: A method for determining elementary circuits and initial values of flows in a pipe network including one or more source nodes and a plurality of demanding nodes. An upstream node and a downstream node of each pipe is determined. The upstream node has less total resistance than the downstream node to the source node. A pipe joined between an upstream node and a downstream node is selected as an upstream pipe of the downstream node. A pipe which is never designated as an upstream pipe is selected as a circuit origin pipe. A node level, which indicates the number of nodes included in the passage from the source node, is determined. An elementary circuit is determined, by tracing upstream nodes along a first route starting from a first node of the circuit origin pipe and along a second route starting from a second node of the circuit origin pipe in accordance with the node level of the upstream node of each pipe, until the first and second routes reach a same source node or a same demanding node.
    Type: Grant
    Filed: May 11, 1993
    Date of Patent: May 9, 1995
    Assignee: Tokyo Gas Co., Ltd
    Inventors: Sakura Shinoaki, Junichi Enomoto
  • Patent number: 5414644
    Abstract: A method of observing and comparing the visual record of repetitive or related events in nature, such as behavioral activities, recorded on a viewable media, which includes converting the visual record into a digital format, storing the digital record in a database at an identifiable location, establishing and storing a textual database comprising written descriptions of the visual record and a glossary of key words identifying repetitive events, the stored information constituting an information library. The library is stored in a microprocessor system, the microprocessor being programmed so that a user can search and retrieve multiple images of a selected event, precursor visual images of events prior to the event in time, responsive activity showing events subsequent to the selected event and contemporaneous events, all retrieved visual images including textual information. The method includes the ability of the user to update, reorder, supplement, and expand the information library as desired.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: May 9, 1995
    Assignee: Ethnographics, Inc.
    Inventors: Gary W. Seaman, Michael Mascha, Homer F. Williams