Patents Examined by Alber Decady
  • Method and apparatus for high speed testing of latch based random access memory
    Patent number: 7231563
    Abstract: A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: June 12, 2007
    Assignee: LSI Corporation
    Inventors: David Vinke, Ekambaram Balaji