Abstract: An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time .PHI.; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: ##EQU1## The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.

Abstract: The apparatus and method for minimization the residual multipath pseudorange error signal present in the received composite spread spectrum signal are disclosed. In the preferred embodiment, the apparatus comprises at least two tracking channels. Each tracking channel includes a generator of a time-varying non-uniform weighting function. Each tracking channel processes an incoming composite signal and outputs a satellite signal and a multipath pseudorange error signal. The tracking channel output signals are scaled by the computer and combined to yield the output signal comprising a satellite signal and a minimized multipath pseudorange error signal in the area of small delays.

Abstract: The present invention is directed to a radio communications apparatus with combining diversity in which received radio signals are weighted appropriately to reduce an error in demodulation and improve in communication quality. In the signal combining diversity radio communications apparatus, the digital reception signals of an intermediate frequency, output from the reception circuit, are demodulated by demodulation circuits into digital demodulation signals of the baseband. The digital demodulation signals are input to the multiplication circuits. The multiplication circuits multiply the digital demodulation signals by the weight coefficients, which are generated by weight coefficient generation circuits and corresponding to the digital demodulation signals, based on C/N ratio detection signals, in order to weight the digital demodulation signals. The weighted demodulation signals are added together by a digital addition circuit.

Abstract: The invention concerns a method and circuitry for compensating internal timing errors of a mobile station, particularly those of a digital mobile station. According to the invention, the signal samples that include the maximum amount of energy and the position signals (maxpos) of these maximum signal samples are, by means of a correlator (8), determined from a channel impulse response estimated in a way known in the art, and in a timing unit (6), with help of successive position signals (maxpos), a correction signal is determined that indicates the magnitude and direction of the timing error of the mobile station, and by said correction signal the ting of the mobile station and particularly that of its clock system is checked and, if necessary, synchronized.

Abstract: A wireless communication subscriber unit comprises a radio frequency downconversion stage that produces in-phase and quadrature phase digital samples. A digital signal processor is connected to receive the samples and process them to produce a control channel correlation output and a carrier frequency offset estimate. The acquisition of the control channel is made substantially immune from initial carrier frequency offsets by differential sample encoding the samples. These are input to a correlator whose coefficients are a pre-stored differential sample encoded, decimated and rate expanded version of the known reference sequence. When the the reference sequence is present, the correlator produces a peak output that can be used to detect the presence of the reference sequence. The time position of the peak can be used for time alignment, for signal quality estimation, and to directly obtain a frequency offset estimate.

Abstract: A secure communications system (501) including a local digital terminal (510) coupled to an interworking function (538). The interworking function (538) couples the digital radio network (121) to a PSTN (542, 546, 548) and a remote analog communication terminal (552). The system (501) includes a novel method of establishing an end-to-end communication channel between local digital (510) and remote analog (552) terminals wherein the local digital terminal establishes (510) a direct digital channel (121) between itself (510) and the interworking function (538) and transmits a message describing its signaling capabilities to the interworking function (538). The interworking function (538) then trains its modem with the modem of the remote analog terminal (552) such that signaling capabilities of the local digital terminal (510) and the remote analog terminal (552) are not violated.

Abstract: A method and apparatus samples (902) a currently received symbol to form sampled values corresponding to sampling times, and evaluates (904) the currently received symbol to determine (906) its value. The method and apparatus recalls (908) a last previously received symbol and selects (916), from a plurality of thresholds (302), a threshold based upon the currently received symbol and the last previously received symbol. The threshold is known to be crossed consistently midway in time between the centers of two adjacent nominal symbols determined by the currently received symbol and the last previously received symbol. The sampled values are compared (920) to locate two adjacent samples, one having a first sampled value greater than the threshold and one having a second sampled value less than or equal to the threshold. A timing phase error is then computed (922, 924) from the first and second sampled values.

Abstract: A method of transmitting and receiving a differential self-clocking data stream. The communications link comprises the coding of information signals onto two signal wires using two logic levels on each wire for a total of four possible coding symbols. The four symbols are utilized to encode data and control-states in both electrically differential and common mode manner upon the two signal wires. The coding sequence is chosen so as to facilitate the communications of binary data and control signals along with demarcation of each successive bit boundary by utilizing the consecutive symbol sequences which are nonrepetitive.