Patents Examined by Albert Deady
  • Patent number: 6871311
    Abstract: A semiconductor integrated circuit device includes a transmitting circuit capable of converting first parallel signals to a first serial signal, a receiving circuit capable of converting a second serial signal to second parallel signals, a test signal generating circuit, and an operation judging circuit, all of which are formed on a single semiconductor chip. The test signal generating circuit and the operation judging circuit are formed so as to operate in accordance with a clock having a frequency corresponding to a transfer rate of the first or second parallel signals.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 22, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Keiki Watanabe, Takashi Harada, Satoshi Ueno