Abstract: The present invention relates to a type of chips radiating structure, there being a radiating plate on the chips on an interface card, and a fixing unit on the radiating plate; wherein said fixing unit has a main unit to be mounted on the radiating plate and a number of pressing arms that extend from the main unit, said pressing arm has a through hole, serving to be inserted by a fastener which penetrates said hole and the fixing hole on the interface card, so that the radiating plate is fastened onto the chips; said fixing unit serves to securely fasten the radiating plate onto the chips, so designed that the radiating plate will quickly dissipate the heat energy generating from the chips, to ensure the normal operation of the chips.

Abstract: Process for making an integrated circuit module and product thereof including a carrier supporting a plurality of precisely aligned semiconductor circuit chips having uniform thicknesses.

Abstract: An integrated circuit and method of use provides conductive vias between conductor layers so that current flows in such a manner that current crowding is reduced in at least one underlying layer. In particular, the current flows from an overlying conductor (306) down to an underlying conductor (303) by a first set of vias (307), and a portion flows through the underlying conductor towards the destination (e.g., a bondpad). Another portion of the current flows downward to a still lower conductor by means of a second set of vias (310, 311). The second set of vias is located further away from the destination than the first set of vias. Current crowding in the underlying conductor is thereby reduced. An integrated circuit utilizing the inventive technique typically has transistors formed in the semiconductor substrate, wherein at least one of the electrodes (e.g.

Abstract: An electrical cartridge of the present invention includes a spring that pushes an integrated circuit package into a thermal plate. The integrated circuit package and substrate are attached to a substrate such as a printed circuit board. A cover may be attached to an opposite side of the substrate. There is typically a space between the integrated circuit package and the thermal plate that is filled with a thermal grease. The spring is located between the cover and the substrate in a manner which deflects the spring and exerts a force on the substrate. The spring force pushes the substrate and the integrated circuit package into the thermal plate. The spring may be designed to always provide a sufficient force to ensure a minimum space between the integrated circuit package and the thermal plate for assemblies produced in a mass production process.

Abstract: A lead frame, method of making same and semiconductor package containing the lead frame. The semiconductor package includes the lead frame which includes an essentially flat, planar lead frame body and lead frame leads extending from the lead frame body, the lead frame leads extending partially out of the plane of the lead frame body. A semiconductor chip is disposed on the lead frame and an encapsulant encapsulates the lead frame body, the semiconductor chip and a portion of the lead frame leads, with a portion of the lead frame leads extending external to the encapsulant. The two dimensional cross section can be essentially in the shape of a "U", essentially sinusoidal in shape, the sinusoidal shape having an odd number of half cycles of the sinusoidal shape or essentially in the shape of a "W".

Abstract: A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

Abstract: Copper foil wiring is applied to base film and the wiring is in turn covered by a cover resist. The electrodes of a semiconductor IC chip is connected to the inner leads of the copper foil wiring and the semiconductor chip is then encapsulated by encapsulation resin. Solder balls are supplied to lands through openings in the cover resist, and bumps are formed. The four sides of the film are then folded to form folded portions. These folded portions increase the strength of the edges of the film, thereby reducing warping and waviness and allowing simultaneous mounting of other devices such as QFP to the substrate. The angle of folding with respect to the film surface is preferably 20.degree. or greater and less than 90.degree., and still greater strength can be obtained by two-stage folding of the sides.

Abstract: A lithographic plate scanner provides more accurate representations of the color intensity of the various image areas of a plate having a fixed image by using only a single photocell to read the solid color bar, the white color bar and the successive image areas in a column of the plate. The readings are stored and a computer compares the image area readings with respect to the color bar readings and determines the amount of ink that must be flowed when the plate is mounted in a printing press to replicate the color in the printing, and stores the same on a floppy disk which is mounted in the printing press computer when the printing occurs.

Abstract: A method and apparatus for electron or laser beam welding of semiconductor subassemblies to larger terminal members, without exposing semiconductor chips in such subassemblies to detrimental welding "flash".