Patents Examined by Alexander Vinnitsky
  • Patent number: 11947427
    Abstract: A method, an electronic device, and a computer program product for storage management are provided. The method includes: acquiring a lock attribute record in a lock attribute record chain from a data protection network for backing up data, data protection servers of the data protection network reaching a consensus on the lock attribute record chain, the lock attribute record including a first attribute value of an attribute of a lock operation, the lock operation being used for preventing a backup of the data stored in a storage server from being tampered with; acquiring, based on the lock attribute record, a second attribute value of the attribute of the lock operation from the storage server; and generating, based on determining that the first attribute value does not match the second attribute value, an alarm indicating that the backup is tampered with. This solution can better prevent data from being tampered with.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 2, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Simon Yuting Zhang, Yizhou Zhou, Aaron Chao Lin
  • Patent number: 11941265
    Abstract: Techniques for managing metadata storage units involve: in response to receiving, from a client, a request for allocating a target number of metadata storage units, determining a first number of available metadata storage units remaining in a metadata storage space of a storage system after the allocation is performed; and if the first number is not less than a reserved number, allocating the target number of metadata storage units from the metadata storage space for the client to use, wherein the reserved number is associated with a usage condition of the metadata storage units in the storage system. Accordingly, such techniques can effectively manage metadata and improve the performance of a system.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 26, 2024
    Assignee: EMC IP Holding Company LLP
    Inventors: Xiongcheng Li, Xinlei Xu, Sihang Xia, Tianshu Sun, Ping Ge
  • Patent number: 11934695
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Dinesh Agarwal, Sharath Shivakumar, Ruchir Sinha
  • Patent number: 11934670
    Abstract: Systems and methods are described for efficiently performing various operations at the granularity of a consistency group (CG) within a cross-site storage solution. An example of one of the various operations includes an independent and parallel resynchronization approach that independently brings individual volumes of a CG to a steady state of in-synchronization (InSync), thereby contributing to scalability of CGs by supporting CGs having a large number of member volumes without requiring a change to the resynchronization process. Another example includes preserving dependent write-order consistency when a remote mirror copy goes out-of-synchronization (OOS) for any reason by driving all member volumes OOS responsive to any member volume becoming OOS. Yet another example includes independent creation of snapshots by member volumes to support efficient and on-demand creation by an application of a common snapshots of all or a subset of peered member volumes of a CG with which the application is associated.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 19, 2024
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Akhil Kaushik, Anoop Vijayan, Omprakash Khandelwal, Arun Kumar Selvam
  • Patent number: 11928030
    Abstract: A method includes creating a deduplicated universal share (US) of data objects, which in turn includes receiving a US of the data objects, deduplicating the US, wherein deduplicating the US includes: hashing segments of the US to generate respective US segment fingerprints; comparing US segment fingerprints to fingerprints for respective segments held in deduplication storage in order to identify segments in the deduplication storage that equate to the US segments, respectively, of the US; storing identifiers that directly or indirectly identify locations, respectively, of the segments, respectively, in the deduplication storage that equate to the US segments, respectively, of the US. After creating the deduplicated universal share, a deduplicated backup of the US is created without reassembling the US from segments held in the deduplication storage, the creating the deduplicated backup including: creating a list that comprises copies of the stored identifiers, and storing the list.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 12, 2024
    Assignee: Veritas Technologies LLC
    Inventors: Shuangmin Zhang, Xianbo Zhang, Shengzhao Li, Xu Jiang, Weibao Wu
  • Patent number: 11914894
    Abstract: Example storage systems, storage devices, and methods provide management of idle time compute tasks from host systems. Storage devices may receive host storage commands for reading and writing host data and host compute commands for executing host compute tasks. Some host compute commands may include a scheduling tag. The storage device may operate in a storage processing state and an idle state and may selectively execute delayed host compute tasks during the idle state.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11907576
    Abstract: A method for communicating with at least one field device via an interface device, wherein each field device is connected to a channel of the interface device, where the method includes receiving a first command associated with a first field device, from an industrial device, communicating with the first field device over a first communication channel for executing the received first command, receiving at least one command associated with the at least one field device, from the industrial device, the at least one commands including at least one command associated with a second field device from the at least one field device, and caching the at least one command in a memory module prior to the execution of the first command.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 20, 2024
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Eric Chemisky, Siva Prasad Katru, Huai Shen Chen, Vishal S
  • Patent number: 11907115
    Abstract: A system includes a memory, a processor in communication with the memory, a hypervisor, and a guest OS. The guest OS is configured to store a plurality of hints in a list at a memory location. Each hint includes an address value and the memory location of the list is included in one of the respective address values associated with the plurality of hints. The guest OS is also configured to pass the list to the hypervisor. Each address value points to a respective memory page of a plurality of memory pages including a first memory page and a last memory page. The hypervisor is configured to free the first memory page pointed to by a first hint of the plurality of hints and free the last memory page pointed to by a second hint of the plurality of hints. Additionally, the last memory page includes the list.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 20, 2024
    Assignee: RED HAT, INC.
    Inventor: Michael Tsirkin
  • Patent number: 11907548
    Abstract: A memory sub-system can allocate a first portion of blocks of a memory device for storage of file system metadata based on a file system and a capacity of the memory device, write video data received from a host within a second portion of the blocks at a first data density, and write file system metadata within the first portion of the blocks at a second data density lesser than the first data density.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Minjian Wu
  • Patent number: 11880599
    Abstract: A memory system includes a memory device and a memory controller. The memory controller transmits a data read command to the memory device, inputs N read enable toggle signals to the memory device in order for the memory device to output the data requested by the data read command requests, and inputs an additional read enable toggle signal to the memory device. The memory device outputs status information of the memory device to the memory controller in response to the additional read enable toggle signal.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeong Jeong, Dae Sung Kim, Sung Ho Ahn
  • Patent number: 11861190
    Abstract: Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 2, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Arash Farhoodfar, Whay Lee
  • Patent number: 11829247
    Abstract: Techniques manage a storage system. Along these lines, a failed storage device is detected among storage devices included in a resource pool of the storage system, and the storage devices belong to a first group and a second group in the resource pool respectively. An extent in the failed storage device assigned for building a stripe in the storage system is determined. A spare reserved extent is selected from respective reserved extents included in respective storage devices among the storage devices based on a mapping relation between the stripe and a plurality of extents in the stripe. The respective reserved extents are shared among the first group and the second group. Data in the extent are rebuilt to the selected spare reserved extent. A reserved storage area can be shared among various storage devices in the resource pool, so as to increase allocatable space in storage devices.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Hongpo Gao, Jian Gao, Xinlei Xu
  • Patent number: 11816355
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 14, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11797178
    Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: October 24, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ramesh Chandra Chaurasiya, Sanish N. Suresh, Clarete Riana Crasta, Sharad Singhal, Porno Shome
  • Patent number: 11775210
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Patent number: 11768629
    Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Nadav Grosz, Roberto Izzi, Jonathan S. Parry
  • Patent number: 11726683
    Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a storage system. A storage system according to an embodiment includes a storage tier including a plurality of storage devices, a cache tier allocated for each of a plurality of storage devices and including a plurality of zone groups each including a hot data zone, a warm data zone, and a cold data zone, a system controller that moves data stored in a source storage device to a target storage device through the cache tier.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: August 15, 2023
    Assignee: SK hynix Inc.
    Inventor: Kyung Soo Lee
  • Patent number: 11726708
    Abstract: Provided herein may be a storage device having improved write performance. The storage device may include a memory device and a memory controller. The memory controller may generate check-in information indicating start of a program operation in response to a write request received from the host, control the memory device to perform a program operation of storing data received from the host in a target area of the memory device, generate check-out information indicating whether the program operation has succeeded, and provide a write result response including the check-out information to the host in response to a write return request received from the host.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 15, 2023
    Assignee: SK hynix Inc.
    Inventor: Eun Soo Jang
  • Patent number: 11687288
    Abstract: A method of queue design for data storage and management applies RAM data synchronization technology on many distributed nodes, both ensures storage performance and solves the problem of data loss in the system operation process; performs business separation and parallelize actions to optimize processing performance; uses simply extracted information instead of accessing the original information helps to speed up the processing ability and promptly detect events that exceed the threshold; allocates a fixed memory for the queue to ensure the safety of the whole system; in addition, provides monitoring and early warning of possible incidents. The method includes: step 1: build a deployment model; step 2: initialize the values when the application first launches; step 3: process write data to the queue; step 4: detect the threshold and process the data in the queue; step 5: remove processed data from the queue; step 6: monitor queue and early warn.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 27, 2023
    Assignee: VIETTEL GROUP
    Inventors: Thanh Phong Pham, The Anh Do, Thi Huyen Dang, Viet Anh Nguyen
  • Patent number: 11662934
    Abstract: A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Steven Leonard Roberts, David A. Larson Stanton, Peter J. Heyrman, Stuart Zachary Jacobs, Christian Pinto