Abstract: A current sensor integrated circuit package includes a primary conductor having an input portion and an output portion, both with reduced area edges. Secondary leads each have an exposed portion and an elongated portion that is offset with respect to the exposed portion. A semiconductor die is disposed adjacent to the primary conductor on an insulator portion and at least one magnetic field sensing element is supported by the semiconductor die. A package body includes a first portion enclosing the semiconductor die and a portion of the primary conductor and a second portion enclosing the elongated portion of the plurality of secondary leads. The first package body portion has a first width configured to expose the input and output portions of the primary conductor and the second package body portion has a second width between a first and second package body side edges that is larger than the first width.

Abstract: An image sensor device and methods of forming the same are described. In some embodiments, the device includes a substrate, a contact pad structure extending from a contact pad region to a black level correction region, a dielectric layer disposed over the substrate in the black level correction region, and a light blocking structure disposed on and through the dielectric layer in the black level correction region. A first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.

Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

Abstract: A semiconductor device includes: a drift region of a first conductivity type arranged between first and second surfaces of a semiconductor body; a first region of the first conductivity type at the second surface; a second region of a second conductivity type arranged adjacent to the first region at the second surface, the second region including first and second sub-regions, the second sub-region arranged between the first sub-region and the second surface; and a first electrode on the second surface and arranged directly adjacent to the first region and the second sub-region. The first electrode is electrically connected to the drift region by the first region. The first sub-region protrudes, along a first lateral direction, over an interface or a separation region between the second sub-region and the first region. A part of the first region is confined by the first sub-region and the first electrode along a vertical direction.

Abstract: A display device includes a pixel in a display area. The pixel may include a first electrode and a second electrode spaced from each other; a first insulating pattern on the first electrode, the first insulating pattern protruding to an outside of the first electrode while having a width greater than that of the first electrode; a second insulating pattern on the second electrode, the second insulating pattern protruding to an outside of the second electrode while having a width greater than that of the second electrode; a light emitting element arranged between the first insulating pattern and the second insulating pattern, the light emitting element including a first end and a second end; a third insulating pattern on a portion of the light emitting element to expose the first end and the second end of the light emitting element; and a first contact electrode on the light emitting element.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located on a source region and a drain region of the etch stop layer.

Abstract: A thyristor memory cell includes a semiconductor cathode, a first un-doped semiconductor feature connected to the semiconductor cathode, a second un-doped semiconductor feature connected to the first un-doped semiconductor feature, a semiconductor anode connected to the second un-doped semiconductor feature, and a gate feature disposed on the first un-doped semiconductor feature or the second un-doped semiconductor feature. Among the semiconductor cathode, the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor anode, the semiconductor anode has the highest bottom edge of conduction band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order; and the semiconductor anode has the highest top edge of the valence band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order.

Abstract: A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.

Abstract: Complementary metal-oxide-semiconductor (CMOS) devices and methods related to selective metal contacts to n-type and p-type source and drain semiconductors are discussed. A p-type metal is deposited on n- and p-type source/drains. The p-type metal is selectively removed from the n-type source/drains but remains on dielectric materials adjacent the n-type source/drains. An n-type metal is deposited on the n-type source/drains while the remaining p-type metal seals the dielectric materials to protect the n-type metal from contamination. The n-type metal is then sealed using another p-type metal. A contact fill material contacts the resultant source and drain contact stacks.

Abstract: Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

Abstract: Described herein are IC devices that include molybdenum or a molybdenum compound, such as compounds including oxygen or nitrogen. The molybdenum may be deposited at a high concentration, e.g., at least 50% atomic density. Also described herein are mid-valent molybdenum precursors for depositing molybdenum, and reactions for producing the mid-valent molybdenum precursors. For example, the molybdenum precursors may be generated by reacting a higher-valent molybdenum compound with an amidinate or a formamidinate.

Abstract: A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

Abstract: A silicon carbide epitaxial layer includes a buffer layer in contact with the silicon carbide substrate, a transition layer disposed on the buffer layer, and a drift layer disposed on the transition layer. An area density of the first defect is a first area density, and an area density of the second defect is a second area density, the first area density is 0.03/cm2 or more, and a value obtained by dividing the second area density by a sum of the first area density and the second area density is less than 2.91%. The first defect, as viewed perpendicularly to the main surface, is shaped to bifurcate from a first origin. No recessed groove is present on an imaginary line segment connecting both ends of the first defect.

Abstract: MRAM device structures and techniques for fabrication thereof with improved dielectric gapfill and individually configurable bottom and top encapsulation layers are provided. In one aspect, an MRAM device includes: memory cell pillars having a diamond shaped profile; and an interlayer dielectric fully filling gaps between the memory cell pillars. For instance, each of the memory cell pillars can include a reference layer, a free layer, a tunnel barrier between the reference layer and the free layer, a first encapsulation layer alongside the reference layer, and a second encapsulation layer alongside the free layer; and an interlayer dielectric fully filling gaps between the memory cell pillars. Optionally, the first encapsulation layer can include an oxide dielectric material, and the second encapsulation layer can include a nitride dielectric material. A method of fabricating the present MRAM devices is also provided.

Abstract: A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.

Abstract: A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a semiconductor substrate, a well region, an isolation structure, a gate structure and a field doped region. The well region having a first conductivity type is disposed in the semiconductor substrate. The gate structure extends to cover a portion of the isolation structure in the well region. The field doped region having a second conductivity type is disposed on the well region. The field doped region has a first portion overlapping the isolation structure and a second portion that is connected to the first portion and away from the gate structure. A first depth between a bottom surface of the first portion and a top surface of the semiconductor structure is greater than a second depth between a bottom surface of the second portion and the top surface of the semiconductor structure.

Abstract: In general, according to one embodiment, a magnetic memory device includes a magnetoresistive effect element. The magnetoresistive effect element includes first to second ferromagnetic layer, a layer stack, and first to third non-magnetic layer. The layer stack is arranged on a side opposite to the first ferromagnetic layer with respect to the second ferromagnetic layer. The third non-magnetic layer is arranged on a side opposite to the second non-magnetic layer with respect to the layer stack and contains a metallic oxide. The layer stack includes a fourth non-magnetic layer being in contact with the third non-magnetic layer and containing platinum (Pt).

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a thermal conductive structure embedded within a first passivation layer of a first wafer, and forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure. The method further includes forming a first connecting structure in contact with the thermal conductive structure and exposed by a surface of the first passivation layer. The method further includes bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer, and bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure.