Abstract: A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.

Abstract: Disclosed herein are methods and apparatus for detecting the presence of a CDPD carrier in a channel of a cellular system (although the invention is broadly applicable to detecting a specific kind of carrier associated with an "overlay" system, wherein an "overlay" system is one that shares the frequency allocation of another system on a non-cooperating basis). This specification describes a spectral estimation technique for detection of a CDPD carrier. In addition, this specification describes an MMSE (minimum mean-squared error) method that improves on the spectral estimation method.

Abstract: A scanner control circuit comprises a digital line delay memory and a control circuit coupled to the digital line delay memory. The control circuit receives digital multi-channel image data having a channel-to-channel delay and corrects for said channel-to-channel delay. Each channel's image data is written into the digital line delay memory at an address in the digital line delay memory corresponding to the correct line number and is then read out of the digital line delay memory for processing. The scanner control circuit operates to allow scanning of an object bi-directionally.

Abstract: Method and apparatus for reducing the contributions of receiver noise signal error and multipath signal error from signals received in a Satellite Positioning System (SATPS) from one or more SATPS satellites by formation and appropriate filtering of differences of signals DD that are differences of SATPS signals received by the SATPS receiver/processor. A difference signal DD of code-phase-derived delta range signals and carrier-phase-derived delta range signals is formed, and this difference signal is passed through a first statistical processing filter with an associated time constant .tau.1 in the approximate range 50-[500] 100 sec, to produce smoothed or filtered signal with the estimated receiver noise error reduced or removed. The difference signal DD is passed through second and third statistical processing filters having associated time constants .tau.2=5-20 sec and .tau.

Abstract: Two line sensors for reading an original are arranged parallel to each other and are moved in a subscanning direction to read an original image. The leading line sensor reads one line on the original, and an output from the leading line sensor is held in analog memories. One line on the original is then read by the trailing line sensor, and an output from the trailing line sensor is added to the output, from the leading line sensor, held in the analog memories, thereby obtaining an effect equivalent to doubled charge storage time in reading one line on the original. A desired resolution can be selected in accordance with the sizes of two sensor elements, the layout of the sensors, and the output timings of the analog memories.

Abstract: A rotationally invariant, multilevel coded modulation scheme is provided by partitioning a constellation, such as an M-PSK or QAM constellation, into several trellis-subsets, each of which is further partitioned into block subsets. The input bits are then encoded to select a signal point from the constellation. A first portion of the input bits are differentially encoded. A second portion of the input bits, together with at least one of the differentially encoded bits, are trellis encoded to select a trellis subset of the constellation. A third portion of the input bits--excluding any differentially encoded bits --are block encoded to select a block subset from the selected trellis subset. A fourth portion of the input bits, together with the remaining differentially encoded bits, are used to select a signal point from the selected block subset.

Abstract: In an image processing apparatus, digital video data is converted into analog video data by a D/A converter. A reference pattern timing-adjusted is generated. The phase relationship between the reference pattern and the analog video data is optimized. The analog video data and the reference pattern are compared by comparing unit. A pulse-width modulated signal output from the comparing unit is detected. The variable output regulator is controlled according to a preset reference value, a quantity of laser light of the output device, or a surface potential of the photoreceptor. Through the control of the regulator, the quantity of bias applied to the reference pattern is optimized at all times, providing a pulse-width modulated image signal with an excellent tone reproduction at all times.

Abstract: Before printing received image data, a facsimile apparatus performs a forcible white data converting operation on a predetermined range of the end regions of lines in the received image data, detects white lines having white data only from the image data subjected to the forcible white data converting operation, and performs the white-line skipping function and the ink donor film saving function based on the result of the white line detection.

Abstract: Image processing method and apparatus for producing an image from image data provides an image memory including a drawing area to store image data of an object to be drawn and a texture area to store texture data to decorate the object, a supply circuit for supplying image data to the image memory, a selector for selectively supplying the image data from the supply circuit to the drawing area and the texture area, an image synthesizing circuit for synthesizing an image from the image data stored in the image memory and an output circuit for converting an output signal from the image synthesizing circuit to a video signal for outputting the video signal. The method provides the steps of storing image data of an object to be drawn in a drawing area of an image memory, storing moving image data in a texture area of the image memory, and mapping a texture of the moving image stored in the texture area onto the surface of the object stored in the drawing area.

Abstract: A image edit apparatus in which area data of 16-bit width have been stored at the memory locations of the corresponding addresses of the respective memory planes of a plane memory 403. The operation of reading area data therefrom by a pseudo sync signal starts before a line sync signal becomes active. A density-conversion/area generating circuit 405 converts the data format from the plane type to the pixel type, so that area commands are generated. Then, the circuit 405 reads an edit command out of a logic RAM, using the area command as address, and outputs the command. By reading the area data earlier and processing that data, a delay in the density-conversion/area generating circuit can be absorbed, so that the output edit command is synchronized with the image data.

Abstract: A digital scanner, which is capable of scanning a document having L scanlines, includes M optical scanning systems wherein M is equal to or greater than 2. Each optical scanning system scans only L/M scanlines of the document such that an area of the document scanned by a single optical scanning system does not overlap an area of the document scanned by another single optical scanning system. The digital scanner also includes a plurality of parallel image processing circuits, each connected to one of the M optical scanning systems, to produce a plurality of sets of digital image data. Each set of image data corresponds to an image scanned by a single optical scanning system. A stitching circuit is connected to the plurality of parallel image processing circuits to stitch together the plurality of sets of digital image data to produce a complete image.

Abstract: An integrated FSK detector circuit includes a first counter that receives a carrier signal and provides a multiple-bit output for reducing the frequency of the carrier signal into a plurality of weighted sub-multiples. An oscillator enable decoder circuit provides predetermined calibrate and measure pulses in response to the first counter output. A gated oscillator receives the calibrate and measure pulses and provides a burst of oscillator pulses during these time intervals. A second counter has an input coupled to the output of the gated oscillator and an up/down control terminal coupled to the output of the first counter. The output of the second counter also provides a multiple-bit output for reducing the frequency of the gated oscillator pulses. An FSK decoder logic circuit decodes the multiple-bit output of the second counter into a single bit FSK detect signal. The FSK detector circuit also includes a reset circuit coupled to the first counter for resetting between FSK detections.

Abstract: Methods for compressing data including methods for compressing highly randomized data are disclosed. Nibble encode, distribution encode, and direct bit encode methods are disclosed for compressing data which is not highly randomized. A randomized data compression routine is also disclosed and is very effective for compressing data which is highly randomized. All of the compression methods disclosed operate on a bit level and accordingly are insensitive to the nature or origination of the data sought to be compressed. Accordingly, the methods of the present invention are universally applicable to any form of data regardless of its source of origination.

Abstract: A method is provided for identifying the frequency of a logic signal that may have a frequency equal to one of n discrete frequencies. The method includes the steps of sequentially transmitting trains of clock pulses of decreasing frequencies. Each clock frequency is a constant multiple of one of the discrete frequencies. The time duration of the first train of clock pulses corresponds to the measurement time duration of a logic signal at the first discrete frequency. The time duration of the i.sup.th train of pulses is such that the sum of the time durations of the first to the i.sup.th pulse trains corresponds to the measurement time duration of a logic signal at the i.sup.th discrete frequency.

Abstract: The present invention is a quantization-level-sampling (QLS) modem which includes means for separately equalizing each loop of an end-to-end digital telephone system network connection by employing a plurality of transmitter filters and a plurality of receiver filters in such a way that, in the direction of transmission from modem to central office, the voltage samples seen by the coder/decoder stations are equivalent to the network quantization levels transmitted by the modem, and in the direction of transmission from central office to modem, the voltage samples seen by the modem are equivalent to the network quantization levels encoded by the coder/decoder stations. The invention also includes a QLS modem communications system which includes the aforesaid digital telephone system network and a plurality of QLS modems. In preferred embodiments, an adaptation service unit within the telephone system network assists in the determination of the settings of the transmitter and receiver filters.

Abstract: Digital image data containing binary pixel values are reproduced, without any loss of detail, by a reproduction unit, such as a laser printer, having a lower base resolution than the resolution of the image data, by subjecting the image data to a resolution conversion, the resolution being reduced in one direction, to a value corresponding to the resolution of the reproduction unit, and enlarged in the remaining direction.

Abstract: A communications system simultaneously transmits both a primary data signal and a secondary voice signal in such a way that the dynamic range of the secondary voice signal is increased even though deliberate errors are introduced into the transmitted data portion of the signal. In particular, the communications system includes an error correcting technique like channel encoding and the constellation signal space is divided into a number of regions, where at least one of the regions overlaps with another region. The primary signal is channel encoded to select a particular one of the number of regions, the region being represented by a reference signal point value. The voice signal is encoded to provide a signal point vector, which is added to the reference signal point in such a way that the resultant signal point is located in the overlapping region thereby deliberately introducing an error into the resulting transmitted signal point stream.

Abstract: A raster scanning system is disclosed which utilizes a post polygon optics which generates a field curvature to substantially reduce a differential bow. The post polygon optics of this invention comprises a first lens, a second lens and a wobble correction mirror. The second lens and the wobble correction mirror generate a field curvature to reduce the differential bow and the combination of the first lens, second lens and the wobble mirror correction minimizes the generated field curvature.

Abstract: An outer symbol error correcting code is concatenated with a punctured multidimensional trellis code to provide an optimal scheme for communicating digital television signals in a standard (e.g., approximately six MHz) bandwidth channel via a cable television network or the like. An input signal is encoded using an outer symbol error correcting code to produce successive blocks. Each block comprises N seven-bit coded symbols of which M represent information to be communicated and the remaining N-M coded symbols comprise error correcting information. M/N is either 120/126, 121/127 or 122/128. The blocks are interleaved, and may be supplemented with control symbols that include a synchronization pattern for M/N=121/127 or M/N=122/128. The interleaved blocks are convolutionally encoded using an inner trellis code having a punctured rate 4/5 (sixty-four QAM) or 3/4 (sixteen QAM). The output symbols are multilevel modulated for transmission over a communication path using, for example, sixteen or sixty-four QAM.

Abstract: When sending electronic mail, a sender designates the payer of the communications fee for the transmission between an electronic mail center and a receiver, that is, the sender or the receiver. When the receiver accesses the electronic mail center, the electronic mail center notifies as the mail summary information for each mail the payer of the fee for the communication between the electronic mail center and the receiver. The fee payer information is displayed on the terminal of the receiver. When the receiver receives from the electronic mail center the electronic mail addressed to him, the electronic mail center generates a bill according to the fee required for the delivery of the electronic mail separately for senders and receivers. In this case, the communications fee for the transmission between the electronic mail center and the receiver is charged to the payer designated by the sender when the electronic mail is sent.