Abstract: A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first conductor layer, second conductor layers, a first semiconductor layer, a pillar, and a contact. The pillar has a portion provided to penetrate the second conductor layers and the first semiconductor layer. The contact is electrically connected to the pillar and the first conductor layer. The pillar includes a second semiconductor layer, a first insulator layer provided at least between the second semiconductor layer and the second conductor layers, and a third semiconductor layer provided between the second semiconductor layer and the first semiconductor layer and in contact with each of the second semiconductor layer and the first semiconductor layer.

Abstract: A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.

Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.

Abstract: Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations.

Abstract: A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Abstract: A memory device includes a first conductor, a first stacked body on the first conductor, a second conductor on the first stacked body, a second stacked body on the second conductor, and a third conductor on the second stacked body. The first stacked body includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in order from a side of the first conductor. The second and third ferromagnetic layers have magnetizations in opposite directions. The second stacked body includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in order from a side of the second conductor. The fifth and sixth ferromagnetic layers have magnetizations in opposite directions. The sixth ferromagnetic layer has a larger volume than the third ferromagnetic layer.

Abstract: A memory device includes peripheral transistors formed along a first surface of a substate; memory cells formed in one or more of first metallization layers disposed over the first surface, each of the memory cells being operatively coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and second metallization layers disposed over a second surface of the substrate opposite to the first surface. A first source/drain terminal of the first reading transistor is in electrical connection with a first source/drain terminal of the programming transistor. A second source/drain terminal of the first reading transistor is in electrical connection with a bit line that is formed in a corresponding one of the second metallization layers.

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

Abstract: An OTP memory using a PUF technology includes a first memory cell. The first memory cell includes an antifuse transistor, a first select transistor and a second select transistor. The antifuse transistor includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first portions of the first nanowire and the second nanowire are contacted with the isolation wall. The second portions of the first nanowire and the second nanowire are covered by the first gate structure. The first drain/source structure is electrically connected with the first terminals of the first nanowire and the second nanowire. The second drain/source structure is electrically connected with a second terminal of the second nanowire, but not electrically connected with a second terminal of the first nanowire.

Abstract: A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.

Abstract: A semiconductor device can include a substrate of semiconductor material and multiple stacks of memory cells disposed within the substrate. Each of the stacks can include a conductive string that connects memory cells to a bitline where each memory cell is located at an intersection of the conductive string and a wordline. The device can also include capacitor having a cylindrical body disposed between two adjacent stacks of memory cells where the capacitor includes an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, where the inner conductive layer and the outer conductive layer are separated by a dielectric layer. The device can further include a power supply line conductively connected to an end of the capacitor at a base of the cylindrical body.

Abstract: An integrated circuit device includes an insulating structure, a source/drain region on the insulating structure, a pair of bottom semiconductor sheets being spaced apart from each other with the source/drain region therebetween in a first horizontal direction, a pair of channel regions spaced apart from the insulating structure with the bottom semiconductor sheets therebetween, a pair of gate lines respectively extending on the pair of channel regions on the bottom semiconductor sheets and extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction, and a backside contact structure extending through the insulating structure to contact a bottom surface of the source/drain region, the backside contact structure including a first contact portion that has a width in the first horizontal direction increasing toward the source/drain region and a second contact portion that has a width in the first horizontal direction decreasing toward the source/drain region.

Abstract: The present disclosure relates to semiconductor packages. An example semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad disposed on a second surface of the second semiconductor chip facing the first surface. The second bonding pad is in contact with the first bonding pad, and includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface. The second semiconductor chip includes a first wiring pad in contact with the fourth surface and a second wiring pad spaced apart from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.

Abstract: Provided are a method for manufacturing a graphene light source, wherein the method includes forming a graphene layer and electrodes in contact with both sides of the graphene layer, forming a nano-gap of the graphene layer, and forming a graphene oxide layer by bonding ionized oxygen to a portion of the graphene layer adjacent to one side of the nano-gap, wherein the graphene oxide layer emits green light or blue light, an organic light emitting element including the graphene light source, and a method for manufacturing the organic light emitting element.

Abstract: The display device includes a light source that generates first light, a conversion layer that outputs a plurality of lights using the first light, and a color filter layer. The conversion layer includes first to third conversion layers, and the color filter layer includes first to third color filters. The first conversion layer and the second conversion layer may include the same material. The first conversion layer and the first color filter may convert the first dominant wavelength of the first light to output second light having a second frequency. The second dominant wavelength of the second light may be located at the first color vertex of the color reproduction rate standard.

Abstract: A light-emitting device with high emission efficiency is provided. The light-emitting device includes a first electrode, a second electrode, and an EL layer positioned between the first electrode and the second electrode. The EL layer includes at least a light-emitting layer, a first layer, a second layer, and a third layer. The first layer is positioned between the first electrode and the light-emitting layer. The third layer is positioned between the first layer and the light-emitting layer. The second layer is positioned between the first layer and the third layer. The first layer includes a first organic compound. The second layer includes a second organic compound. The third layer includes a third organic compound. The ordinary refractive index of the second organic compound is higher than the ordinary refractive index of the first organic and the ordinary refractive index of the third organic compound.

Abstract: An integrated circuit (IC) device includes a substrate, a bottom semiconductor device over the substrate, and a top semiconductor device over the bottom semiconductor device in a thickness direction of the substrate. The top semiconductor device and the bottom semiconductor device are of a same conductivity type.

Abstract: A semiconductor device including a substrate, an interfacial layer on the substrate, a ferroelectric layer on the interfacial layer, a gate on the ferroelectric layer, and the nitride protective layer between the interfacial layer and the gate and being adjacent to the ferroelectric layer.