Abstract: Methods, apparatus, systems, and articles of manufacture to reduce impedance discontinuities and crosstalk in integrated circuit packages are disclosed. A disclosed apparatus includes: a package substrate, and a ball grid array on a first surface of the package substrate. The ball grid array includes a first ball and a second ball adjacent the first ball. The ball grid array is to enable the package substrate to be electrically coupled to a circuit board. The apparatus further includes a metal interconnect within the package substrate. The metal interconnect is electrically coupled to the first ball. The metal interconnect includes an inductive loop that extends toward the second ball.

Abstract: An integrated circuit (IC) includes a first metal layer that provides a signal layer. The IC furthermore includes a second metal layer spaced apart from the first metal layer by a gap, the second metal layer providing a ground plane. A meshed signal line including one or more holes is disposed in the first metal layer and the meshed signal line is configured to transmit a received signal between circuits on the IC.

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

Abstract: An image sensor includes a substrate including a first pixel, a second pixel, a device isolation pattern, and at least one open region, wherein each of the first pixel and the second pixel includes a first pixel region including a first photoelectric conversion device and a second pixel region including a second photoelectric conversion device, the second pixel region being parallel with the first pixel region in a first direction, and wherein the device isolation pattern includes a first portion between the first pixel region and the second pixel region of the first pixel and between the first pixel region and the second pixel region of the second pixel, a second portion between the first pixel region of the first pixel and the first pixel region of the second pixel, and a third portion between the second pixel region of the first pixel and the second pixel region of the second pixel.

Abstract: A semiconductor device includes multiple transistors formed in a substrate, a frontside power rail disposed on a frontside of the substrate, and a backside power rail disposed on a backside of the substrate. The transistors form at least a first cell functioning under a first power supply voltage and a second cell functioning under a second power supply voltage that is different from the first power supply voltage. The frontside power rail provides the first power supply voltage to the first cell, and the backside power rail provides the second power supply voltage to the second cell.

Abstract: A semiconductor device includes first power lines extending on a substrate in a first direction and spaced apart from each other in a second direction, back side power structures on a lower surface of the substrate, standard cells each including an active pattern, a gate pattern intersecting the active pattern, and contacts, power tap cells between at least some of the standard cells and each including vertical power vias, and second power lines electrically connecting at least some of the first power lines to each other. A first portion of the second power lines may extend onto the power tap cells and a second portion of the second power lines that is different from the first portion may extend onto the standard cells. The power tap cells may be arranged in every three or more rows of the standard cells in the second direction in a zigzag pattern.

Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.

Abstract: A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first conductor layer, second conductor layers, a first semiconductor layer, a pillar, and a contact. The pillar has a portion provided to penetrate the second conductor layers and the first semiconductor layer. The contact is electrically connected to the pillar and the first conductor layer. The pillar includes a second semiconductor layer, a first insulator layer provided at least between the second semiconductor layer and the second conductor layers, and a third semiconductor layer provided between the second semiconductor layer and the first semiconductor layer and in contact with each of the second semiconductor layer and the first semiconductor layer.

Abstract: A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.

Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.

Abstract: Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations.

Abstract: A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Abstract: A memory device includes a first conductor, a first stacked body on the first conductor, a second conductor on the first stacked body, a second stacked body on the second conductor, and a third conductor on the second stacked body. The first stacked body includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in order from a side of the first conductor. The second and third ferromagnetic layers have magnetizations in opposite directions. The second stacked body includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in order from a side of the second conductor. The fifth and sixth ferromagnetic layers have magnetizations in opposite directions. The sixth ferromagnetic layer has a larger volume than the third ferromagnetic layer.

Abstract: A memory device includes peripheral transistors formed along a first surface of a substate; memory cells formed in one or more of first metallization layers disposed over the first surface, each of the memory cells being operatively coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and second metallization layers disposed over a second surface of the substrate opposite to the first surface. A first source/drain terminal of the first reading transistor is in electrical connection with a first source/drain terminal of the programming transistor. A second source/drain terminal of the first reading transistor is in electrical connection with a bit line that is formed in a corresponding one of the second metallization layers.

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

Abstract: An OTP memory using a PUF technology includes a first memory cell. The first memory cell includes an antifuse transistor, a first select transistor and a second select transistor. The antifuse transistor includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first portions of the first nanowire and the second nanowire are contacted with the isolation wall. The second portions of the first nanowire and the second nanowire are covered by the first gate structure. The first drain/source structure is electrically connected with the first terminals of the first nanowire and the second nanowire. The second drain/source structure is electrically connected with a second terminal of the second nanowire, but not electrically connected with a second terminal of the first nanowire.

Abstract: A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.

Abstract: A semiconductor device can include a substrate of semiconductor material and multiple stacks of memory cells disposed within the substrate. Each of the stacks can include a conductive string that connects memory cells to a bitline where each memory cell is located at an intersection of the conductive string and a wordline. The device can also include capacitor having a cylindrical body disposed between two adjacent stacks of memory cells where the capacitor includes an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, where the inner conductive layer and the outer conductive layer are separated by a dielectric layer. The device can further include a power supply line conductively connected to an end of the capacitor at a base of the cylindrical body.

Abstract: An integrated circuit device includes an insulating structure, a source/drain region on the insulating structure, a pair of bottom semiconductor sheets being spaced apart from each other with the source/drain region therebetween in a first horizontal direction, a pair of channel regions spaced apart from the insulating structure with the bottom semiconductor sheets therebetween, a pair of gate lines respectively extending on the pair of channel regions on the bottom semiconductor sheets and extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction, and a backside contact structure extending through the insulating structure to contact a bottom surface of the source/drain region, the backside contact structure including a first contact portion that has a width in the first horizontal direction increasing toward the source/drain region and a second contact portion that has a width in the first horizontal direction decreasing toward the source/drain region.