Abstract: The present disclosure relates to semiconductor packages. An example semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad disposed on a second surface of the second semiconductor chip facing the first surface. The second bonding pad is in contact with the first bonding pad, and includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface. The second semiconductor chip includes a first wiring pad in contact with the fourth surface and a second wiring pad spaced apart from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.

Abstract: Provided are a method for manufacturing a graphene light source, wherein the method includes forming a graphene layer and electrodes in contact with both sides of the graphene layer, forming a nano-gap of the graphene layer, and forming a graphene oxide layer by bonding ionized oxygen to a portion of the graphene layer adjacent to one side of the nano-gap, wherein the graphene oxide layer emits green light or blue light, an organic light emitting element including the graphene light source, and a method for manufacturing the organic light emitting element.

Abstract: The display device includes a light source that generates first light, a conversion layer that outputs a plurality of lights using the first light, and a color filter layer. The conversion layer includes first to third conversion layers, and the color filter layer includes first to third color filters. The first conversion layer and the second conversion layer may include the same material. The first conversion layer and the first color filter may convert the first dominant wavelength of the first light to output second light having a second frequency. The second dominant wavelength of the second light may be located at the first color vertex of the color reproduction rate standard.

Abstract: A light-emitting device with high emission efficiency is provided. The light-emitting device includes a first electrode, a second electrode, and an EL layer positioned between the first electrode and the second electrode. The EL layer includes at least a light-emitting layer, a first layer, a second layer, and a third layer. The first layer is positioned between the first electrode and the light-emitting layer. The third layer is positioned between the first layer and the light-emitting layer. The second layer is positioned between the first layer and the third layer. The first layer includes a first organic compound. The second layer includes a second organic compound. The third layer includes a third organic compound. The ordinary refractive index of the second organic compound is higher than the ordinary refractive index of the first organic and the ordinary refractive index of the third organic compound.

Abstract: An integrated circuit (IC) device includes a substrate, a bottom semiconductor device over the substrate, and a top semiconductor device over the bottom semiconductor device in a thickness direction of the substrate. The top semiconductor device and the bottom semiconductor device are of a same conductivity type.

Abstract: A semiconductor device including a substrate, an interfacial layer on the substrate, a ferroelectric layer on the interfacial layer, a gate on the ferroelectric layer, and the nitride protective layer between the interfacial layer and the gate and being adjacent to the ferroelectric layer.

Abstract: An integrated circuit device includes an insulating structure, a source/drain region on the insulating structure, a pair of bottom semiconductor sheets being spaced apart from each other with the source/drain region therebetween in a first horizontal direction, a pair of channel regions spaced apart from the insulating structure with the bottom semiconductor sheets therebetween, a pair of gate lines respectively extending on the pair of channel regions on the bottom semiconductor sheets and extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction, and a backside contact structure extending through the insulating structure to contact a bottom surface of the source/drain region, the backside contact structure including a first contact portion that has a width in the first horizontal direction increasing toward the source/drain region and a second contact portion that has a width in the first horizontal direction decreasing toward the source/drain region.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.

Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.

Abstract: A memory device is disclosed. The memory device includes a plurality of one-time programmable (OTP) memory cells. Each OTP memory cell includes a transistor disposed on a first side of a substrate, and a capacitor disposed on a second side of the substrate opposite to the first side and electrically connected to the transistor. The capacitor includes a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer vertically interposed therebetween.

Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: A MRAM layout is provided in the present invention, wherein each memory cell includes a first word line, a third word line and a second word line spaced apart on a substrate in order and extending in a first direction over active areas, a first MTJ in BEOL metal layers with one terminal connected to a second active area and another terminal connected to a first bit line, a second MTJ in the BEOL metal layer with one terminal connected to a third active area and another terminal connected to a second bit line, wherein the first bit line and the second bit line are in different metal levels of the BEOL metal layer, and a source line is connected to a first active area and a fourth active area.

Abstract: A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.

Abstract: A memory device includes a first outer support structure extending along a first direction. The memory device also includes a first protrusion pattern extending along the first direction, the first protrusion pattern being in contact with an end of the first outer support structure. The memory device further includes a connection support structure spaced apart from the first protrusion pattern along a second direction perpendicular to the first direction. The memory device additionally includes a first oblique support structure connecting the connection support structure and the first outer support structure to each other in an oblique direction to the first and second directions.

Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

Abstract: A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.