Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.

Abstract: A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures.

Abstract: An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Abstract: There is provided a method for producing a nitride semiconductor laminate in which a thin film is homoepitaxially grown on a substrate comprising group III nitride semiconductor crystals, the method including: homoepitaxially growing a thin film on a substrate, using the substrate in which a dislocation density on its main surface is 5×106 pieces/cm2 or less, a concentration of oxygen therein is less than 1×1017 at·cm?3, and a concentration of impurities therein other than n-type impurity is less than 1×1017 at ·cm?3; and inspecting a film quality of the thin film formed on the substrate, wherein in the inspection of the film quality, the film quality of the thin film is inspected by detecting a deviation of an amount of reflected light at a predetermined wavenumber determined in a range of 1,600 cm?1 or more and 1,700 cm?1 or less in a reflection spectrum obtained by irradiating the thin film on the substrate with infrared light, from an amount of reflected light at the predetermined wavenumber determined ac

Abstract: A phase-change memory device and method of manufacturing the same, the memory device including: a substrate; a bottom electrode disposed over the substrate; a top electrode disposed over the bottom electrode; and a phase-change layer disposed between the top and bottom electrodes. The phase change layer includes a chalcogenide Ge—Sb—Te (GST) material that includes at least 30 at % Ge and that is doped with a dopant including N, Si, Sc, Ga, C, or any combination thereof.

Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.

Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.

Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop f

Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.

Abstract: In a light detection device, the light detection unit includes an APD, a plurality of temperature compensation diodes, and a terminal electrically connecting the APD and the plurality of temperature compensation diodes in parallel with each other. The plurality of temperature compensation diodes is configured to provide temperature compensation for the gain of the APD. The light detection unit has a light detection region and temperature detection regions. The APD is provided in the light detection region. The temperature detection regions are located around the light detection region. The plurality of temperature compensation diodes are provided in the temperature detection regions. The light detection region is interposed between the temperature detection region and the temperature detection region.

Abstract: A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Abstract: A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.

Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Abstract: A resistance change device of an embodiment includes: a first electrode; a second electrode; and a stack disposed between these electrodes, and including a first layer containing a resistance change material and a second layer in contact with the first layer. The resistance change material contains at least one of a first element such as Ge and a second element such as Sb, and at least one third element selected from Te, Se, S, and O. The second layer contains a crystal material containing at least one selected from a group consisting of a first material having a composition represented by (Ti,Zr,Hf)CoSb, (Zr,Hf)NiSn, or Fe(Nb,Zr,Hf)(Sb,Sn), a second material having a composition represented by Fe(V,Hf,W)(Al,Si), and a third material having a composition represented by Mg(Si,Ge,Sn).

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.