Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail.

Abstract: A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts.

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A method for preparing a semiconductor structure includes: providing a substrate which includes a device region and a shallow trench isolation region surrounding the device region, in which the device region is exposed from a surface of the substrate; depositing a barrier layer on the substrate, the barrier layer at least covering the device region; forming an initial oxide which is located in the device region and in contact with the barrier layer; and removing part of the initial oxide to form a device oxide.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

Abstract: The disclosure belongs to the field of micro-nano electronic materials, and in particular to a Se-based selector material, a selector unit, and a preparation method thereof. The Se-based selector material is a compound including Ge, Se, and B elements. The chemical formula of the Se-based selector material is (GexSe1?x)1?yByMz, in which the M element is at least one of In, Ga, Al, and Zn, and 0.1?x?0.9, 0.02?y?0.15, and 0?z?0.2. The problems of safety and stability of the existing material selection for the selector are solved by the selector material, the selector unit, and the preparation method thereof provided by the disclosure. In addition, the threshold voltage of the selector device prepared based on the Se-based selector material is adjustable, and the comprehensive performance is good.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first dielectric layer on a substrate; first/second upper short axis portions extending along a first direction, separated from each other, and on the first dielectric layer; a common source region in the substrate and adjacent to the first/second upper short axis portions; a first branch drain region in the substrate, adjacent to the first upper short axis portion, and opposite to the common source region; a second branch drain region in the substrate, adjacent to the second upper short axis portion, and opposite to the common source region; and a top electrode on the first dielectric layer and topographically above the first branch drain region and the second branch drain region. The top electrode, the first dielectric layer, and the first/second branch drain regions together configure a programmable unit.

Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A semiconductor device includes a substrate having a first area and a second area. The semiconductor device in the first area includes a first memory layer and a first semiconductor channel coupled to a portion of the first memory layer. The semiconductor device in the first area further includes a first conductive structure and a second conductive structure coupled to end portions of the first semiconductor channel. The semiconductor device in the second area includes a third conductive structure and a second memory layer. The semiconductor device in the second area includes a second semiconductor channel that comprises: (i) a first vertical portion coupled to a portion of the second memory layer; and (ii) a lateral portion coupled to a top surface of the third conductive structure. The semiconductor device in the second area includes a fourth conductive structure coupled to an end portion of the second semiconductor channel.

Abstract: This invention provides a stacked neuron device structure and a manufacturing method thereof. The device comprises: a substrate with peripheral circuits in the substrate; a barrier layer; a neuron transistor array, comprising a plurality of neuron transistors arranged in an array, wherein the transistor comprises a semiconductor channel, a modulation stack, and a gate array; the two ends of the semiconductor channel are respectively connected to peripheral circuits, and the peripheral circuit is used to control the gating or closing of the corresponding neuron transistor. The first dielectric layer, the weighting floating gate layer and the second dielectric layer are stacked in this order. The gate array is located on the modulation stack and is used to modulate the potential of the weighting floating gate to realize the weighting of the weight floating gate.

Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth m

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.