Abstract: A semiconductor device includes a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate, a passivation layer between the source and drain electrodes, a gate electrode between the source and drain electrodes, and a conductive field plate adjacent to the gate electrode. The passivation layer includes a lower passivation sub-layer and an upper passivation sub-layer over the lower passivation sub-layer. The gate electrode includes a lower portion that extends at least partially through the passivation layer. The conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer. The conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: A MRAM layout is provided in the present invention, wherein each memory cell includes a first word line, a third word line and a second word line spaced apart on a substrate in order and extending in a first direction over active areas, a first MTJ in BEOL metal layers with one terminal connected to a second active area and another terminal connected to a first bit line, a second MTJ in the BEOL metal layer with one terminal connected to a third active area and another terminal connected to a second bit line, wherein the first bit line and the second bit line are in different metal levels of the BEOL metal layer, and a source line is connected to a first active area and a fourth active area.

Abstract: A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.

Abstract: A memory device includes a first outer support structure extending along a first direction. The memory device also includes a first protrusion pattern extending along the first direction, the first protrusion pattern being in contact with an end of the first outer support structure. The memory device further includes a connection support structure spaced apart from the first protrusion pattern along a second direction perpendicular to the first direction. The memory device additionally includes a first oblique support structure connecting the connection support structure and the first outer support structure to each other in an oblique direction to the first and second directions.

Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

Abstract: A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

Abstract: A memory device includes a memory array die corresponding to a memory array, an access circuitry die corresponding to peripheral circuitry to support access operations with respect to the memory array, and a bonding layer disposed between the memory array die and the access circuitry die to form an interconnection between the memory array and the access circuitry. In some embodiments, the access circuitry die further integrates a local media controller corresponding to the memory array. In some embodiments, the local media controller is located external to the access circuitry die.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

Abstract: A dual-port memory cell includes a first, second, third, and fourth pass-gate transistor, and a first and a second word line. The first pass-gate transistor includes a first gate on a first level. The second pass-gate transistor includes a second gate on a second level below the first level. The third pass-gate transistor includes a third gate on the first level. The fourth pass-gate transistor includes a fourth gate on the second level. The first word line is on a first metal layer above a front-side of a substrate, and is coupled to the first and third pass-gate transistors that correspond to a first port of the dual-port memory cell. The second word line is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth pass-gate transistors that correspond to a second port of the dual-port memory cell.

Abstract: A semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).

Abstract: A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.

Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

Abstract: An example thin-film transistor includes a source, a drain, a gate, and a body of channel material disposed within the influence of the gate between the source and the drain. The body of channel material includes a metal oxide. The body of channel material forms a carrier channel between the source and the drain when sufficient voltage is applied to the gate. The source includes a body of source material that includes ruthenium and an oxide-stabilizing metal that has an oxide that has greater hydrogen stability than ruthenium oxide.

Abstract: A display apparatus having an image capturing function is provided. A display apparatus or an imaging device with a high aperture ratio is provided. The display apparatus includes a first light-emitting element and a light-receiving element. The first light-emitting element is formed by stacking a first pixel electrode, a first organic layer, and a common electrode in this order. The light-receiving element is formed by stacking a second pixel electrode, a second organic layer, and the common electrode in this order. The first organic layer includes a first light-emitting layer, and the second organic layer includes a photoelectric conversion layer. A first layer and a second layer are included in a region between the first light-emitting element and the light-receiving element. The first layer overlaps with the second organic layer and contains the same material as the first organic layer. The second layer overlaps with the first organic layer and contains the same material as the second organic layer.