Patents Examined by Almis Jankos
  • Patent number: 5392392
    Abstract: A parallel polygon/pixel rendering engine for a digital map capable of producing real-time linear shaded, three dimensional, raster graphics for video generation. The apparatus is suitable for use with avionic display systems, particularly digital map displays which include an instruction and interpreter unit and an image scanner. The apparatus comprises a raster engine, a memory interface and a bit mapped memory. The raster engine further includes a raster engine control and generic interpolation polygon processor interface, an edge interpolator, a line interpolator and a controller for the edge and line interpolators. The raster engine control is electrically connected to receive data from the instruction interface unit and is further electrically connected to the edge interpolator and interpolator controller. The edge interpolator is adapted to receive data from the raster engine control and the line interpolator is electrically connected to receive data from the edge interpolator.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: February 21, 1995
    Assignee: Honeywell Inc.
    Inventors: Douglas A. Fischer, Jennifer A. Graves, Thomas D. Snodgrass
  • Patent number: 5287440
    Abstract: A graphic processing device is composed of a main storage device, a drawing control device and a drawing device. The main storage device stores data relative to the coordinates of plural graphics. The drawing control device reads out the data relative to the coordinates of the plural graphics stored in the main storage device, scans the coordinate data to calculate the coordinates of intersecting points of a scanning line and the plural graphics for each position of the scanning line. The drawing control device also determines an overlapping area (AND area) or a common area (OR area) of the plural graphics on the basis of the coordinates of the intersecting points of the plural graphics and the scanning line. The drawing device draws the overlapping area (AND area) and the common area (OR area) of the plural graphics as a graphic.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: February 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kimiya Yamaashi, Shuuichi Miura, Yuji Taki, Atsushi Kawabata
  • Patent number: 5280571
    Abstract: A method and apparatus for creating computer generated lines using a single or multiple instruction multiple data processor in conjunction with a modified version of Bresenham's line drawing algorithm wherein the speed of the operation is enhanced by allowing the processor to perform its memory writes in page mode.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: January 18, 1994
    Assignee: Intel Corporation
    Inventors: Michael Keith, Yaron Minsky
  • Patent number: 5228124
    Abstract: In a reader in which a tablet and a cursor device are connected electrically to the reader and an indicated position of the cursor device on the tablet is converted to a coordinate signal to be outputted, the improved reader in which two cursor devices are connected to the reader, and the first cursor device is retained by one hand, and the second cursor device is retained by the other hand, and the two cursor devices are manipulated by both hands of the operator so as to shift them on the tablet whereby the reader outputs the coordinate signal for the drawing of a graphic, and setting the command to a CPU on the basis of the indication of each cursor device.
    Type: Grant
    Filed: December 3, 1991
    Date of Patent: July 13, 1993
    Assignee: Mutoh Industries, Ltd.
    Inventors: Ichiki Kaga, Tatsuyoshi Ikuta, Hiroyuki Furuichi, Shuzo Matsumoto, Tetsuya Iwanaga
  • Patent number: 5179639
    Abstract: A multiple memory display controller provides simultaneous display of overlaid image and graphic data in a computer display system. A video random access memory (RAM) in the display controller stores display data corresponding to graphics to be displayed on the computer display monitor. And a series of dynamic RAMS in the display controller stores display data corresponding to images to be displayed on the computer display monitor. A data mixer receives and mixes signals from the video RAM and one of the dynamic RAMs to form signals which are used to drive the display monitor. The signals provide graphics displayed at one resolution overlaid on images displayed at a different resolution on the monitor. A first-in first-out (FIFO) buffer and rectangle loader provide efficient loading of blocks of display data in the display controller memories.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: January 12, 1993
    Assignee: Massachusetts General Hospital
    Inventor: James L. Taaffe