Patents Examined by Alva C. Powell
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Patent number: 5994227Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.Type: GrantFiled: July 20, 1998Date of Patent: November 30, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
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Patent number: 5989445Abstract: Microchannels for conducting and expelling a fluid are embedded in a surface of a silicon substrate. A channel seal is made of plural cross structures formed integrally with the silicon substrate. The cross structures are arranged sequentially over each channel, each cross structure having a chevron shape. The microchannel is sealed by oxidizing at least partially the cross structures, whereby the spaces therebetween are filled. A dielectric seal which overlies the thermally oxidized cross structures forms a complete seal and a substantially planar top surface to the silicon substrate. The dielectric seal is formed of a low pressure chemical vapor deposition (LPCVD) dielectric layer. The channel is useful in the production of an ink jet print in head, and has a polysilicon heater overlying the dielectric seal. A current passing through the heater causes a corresponding increase in the temperature of the ink in the microchannel, causing same to be expelled therefreom.Type: GrantFiled: June 17, 1998Date of Patent: November 23, 1999Assignee: The Regents of the University of MichiganInventors: Kensall D. Wise, Jingkuang Chen
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Patent number: 5990003Abstract: There is provided a method of fabricating a semiconductor, including the steps, in sequence, of (a) forming a first interlayer insulating film over a semiconductor substrate, (b) forming an electrically conductive contact hole in the first interlayer insulating film, (c) forming a second interlayer insulating film over the first interlayer insulating film, (d) forming a photosensitive organic film over the second interlayer insulating film, (e) forming a via-hole passing through the photosensitive organic film and the second interlayer insulating film, the via-hole being in vertical alignment with the contact hole, (f) forming a film so that the film covers the photosensitive organic film therewith and fills the via-hole therewith, (g) exposing the film to plasma so that a portion of the film lying over the photosensitive organic film is removed, (h) removing both the photosensitive organic film and the film remaining in the via-hole, and (i) forming a wire above the via-hole.Type: GrantFiled: April 23, 1997Date of Patent: November 23, 1999Assignee: NEC CorporationInventor: Noriaki Oda
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Patent number: 5985094Abstract: The carrier assembly includes an internal pressurized fluid circuit which places an incompressible fluid layer between a pressure plate and an internal diaphragm. The internal diaphragm has a flexible portion providing gimbal action for the carrier assembly. The diaphragm and hydrostatic forces of the internal fluid circuitry combine to form a gimbal action exhibiting low friction, but which is otherwise rigid in other axes.Type: GrantFiled: May 12, 1998Date of Patent: November 16, 1999Assignee: Speedfam-IPEC CorporationInventor: Joseph Mosca
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Patent number: 5968374Abstract: A method in a variable-gap plasma processing chamber for controlled removal of at least a portion of an upper crust of a photoresist layer disposed above a substrate. The upper crust represents a hardened upper layer of the photoresist layer. The method includes loading the substrate into the variable-gap plasma processing chamber. The method further includes flowing an ash source gas comprising O.sub.2 into the variable-gap plasma processing chamber. The ash source gas is substantially free of an O.sub.2 bombarding gas. The method further includes performing the controlled removal of at least the portion of the upper crust of the photoresist layer with a plasma struck from the ash source gas while a gap between an upper surface of the substrate and an upper electrode of the variable-gap plasma processing chamber is maintained at a predefined wide gap distance.Type: GrantFiled: March 20, 1997Date of Patent: October 19, 1999Assignee: Lam Research CorporationInventor: David M. Bullock
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Patent number: 5961725Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.Type: GrantFiled: June 8, 1998Date of Patent: October 5, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Lang Wang, Yu-Jen Yu
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Patent number: 5958140Abstract: A one-by-one type heat-processing apparatus is disclosed. The one-by-one type heat-processing apparatus includes a processing vessel for processing a semiconductor wafer. A susceptor having a support surface for placing the semiconductor wafer is arranged in the processing vessel. A shower head section is arranged at an interval with respect to the support surface of the susceptor. Processing gas supply pipes for supplying a processing gas are independently connected to the shower head section. A plurality of gas injection holes are formed in the shower head section. First to third heating means for heating the susceptor are attached to the susceptor. The first heating means having a disk-like shape is arranged at almost the center on the lower surface side of the susceptor. The second heating means is concentrically arranged to surround the first heating means. The third heating means is arranged at the peripheral edge portion of the susceptor.Type: GrantFiled: July 26, 1996Date of Patent: September 28, 1999Assignee: Tokyo Electron LimitedInventors: Junichi Arami, Kenji Ishikawa, Masayuki Kitamura
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Abrasive pad and manufacturing method thereof and substrate polishing method using said abrasive pad
Patent number: 5944589Abstract: An abrasive pad whose abrasive surface has recesses that allow abrasive slurry to stay there is used instead of forming scratches on the abrasive surface of an abrasive pad. This eliminates a dressing operation for forming innumerable scratches on the abrasive surface of an abrasive pad in polishing a wafer. Omitting a dressing step from a wafer polishing process lowers the degree of impurity contamination of a wafer, and eliminating a dresser from a polishing apparatus reduces its cost.Type: GrantFiled: February 13, 1998Date of Patent: August 31, 1999Assignee: Sony CorporationInventor: Hideharu Nakajima -
Patent number: 5935452Abstract: A resin composition comprising (a) an epoxy resin having a number average molecular weight of 1200 or less, (b) a carboxylic acid-containing acrylic or acrylonitrile-butadiene rubber, (c) a curing agent for the epoxy resin, and (d) a curing accelerator is easily chemically etched and suitable as an insulating adhesive for producing multilayer printed circuit boards.Type: GrantFiled: November 10, 1998Date of Patent: August 10, 1999Assignee: Hitachi Chemical Company, Ltd.Inventors: Teiichi Inada, Yoshiyuki Tsuru, Shin Takanezawa
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Patent number: 5932485Abstract: Disclosed is a process for exposing a metal-containing surface feature on an integrated circuit wafer by laser ablation. According to the invention, a silicon dioxide passivation layer is provided upon the surface feature. The silicon dioxide layer is transparent to electromagnetic radiation having a specified wavelength, such that the electromagnetic radiation is directed through the silicon dioxide layer onto the underlying surface feature. A portion of the surface feature is ablated. Ablation of the surface feature causes removal of an overlying portion of the silicon dioxide layer, thereby exposing the surface feature. Laser ablation may further be performed on optional overlying layers of silicon nitride and polyimide.Type: GrantFiled: October 21, 1997Date of Patent: August 3, 1999Assignee: Micron Technology, Inc.Inventor: Kevin H. Schofield
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Patent number: 5933706Abstract: A method for treatment of the surface of a CdZnTe (CZT) crystal that reduces surface roughness (increases surface planarity) and provides an oxide coating to reduce surface leakage currents and thereby, improve resolution. A two step process is disclosed, etching the surface of a CZT crystal with a solution of lactic acid and bromine in ethylene glycol, following the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, oxidizing the CZT crystal surface.Type: GrantFiled: May 28, 1997Date of Patent: August 3, 1999Inventors: Ralph James, Arnold Burger, Kuo-Tong Chen, Henry Chang
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Patent number: 5932061Abstract: A system that decapsulates an integrated circuit package while the package is mounted to a printed circuit board. The system includes a tray that supports a printed circuit board which has at least one integrated circuit package mounted to the board. Mounted to the tray is a clamp which clamps an injection head to the top of the package. The injection head is coupled to a source of decapsulation fluid which is sprayed onto the package. The decapsulation fluid is circulated across the package to remove the package material and expose the underlying integrated circuit. The injection head has a gasket that is pressed onto the package to prevent the fluid from leaking onto the printed circuit board. After the plastic is decapsulated the head can be removed from the package so that the integrated circuit can be tested while the circuit is connected to the printed circuit board.Type: GrantFiled: October 29, 1996Date of Patent: August 3, 1999Assignee: Sun Microsystems, Inc.Inventor: Chung Lam
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Patent number: 5925576Abstract: A plug for plugging selected perforations in a carrier assembly used in a chemical mechanical polishing system for polishing semiconductor wafers is disclosed. The plug comprises a pressure-resistant portion; a bottom portion attached to the pressure-resistant portion; and a leak-resistant portion extending from the pressure-resistant portion, dimensioned to fit snugly into the bottom portion.Type: GrantFiled: August 19, 1998Date of Patent: July 20, 1999Assignee: ProMOS Technologies, Inc.Inventor: Cheng-An Peng
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Patent number: 5919379Abstract: Copper foil having a matte surface and an opposite shiny surface, the shiny surface having thereon a protective metallic coating comprised of a first protective metallic layer, preferably iron, electrodeposited on the shiny surface and a second metallic layer, preferably zinc, electrodeposited on the first layer, the metallic coating be chemically removable without damage to the copper foil and the second metallic layer being softer than the first metallic layer. The matte surface of the copper foil can be bonded to a dielectric material, and the protective metallic coating can be removed from the shiny surface by etching.Type: GrantFiled: December 22, 1997Date of Patent: July 6, 1999Assignee: Foil Technology Development CorporationInventor: John E. Thorpe
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Patent number: 5919715Abstract: An improved method for cleaning a group III-nitride-based semiconductor surface prior to depositing electrodes or growing additional layers of semiconductor. In a cleaning method according to the present invention, the surface of the semiconductor is brought into contact with an etchant solution that includes hydrofluoric acid. The etching step is preferably carried out at a HF concentration greater than 5% and at a temperature between 10 to 100.degree. C. in an inert atmosphere. The etchant solution may also include other acids. Group III-nitride semiconductor devices cleaned in this manner require lower driving voltages than devices cleaned with prior art methods.Type: GrantFiled: February 4, 1998Date of Patent: July 6, 1999Assignee: Hewlett-Packard CompanyInventors: Tetsuya Tekeuchi, Yawara Kaneko
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Patent number: 5916365Abstract: The present invention provides for sequential chemical vapor deposition by employing a reactor operated at low pressure, a pump to remove excess reactants, and a line to introduce gas into the reactor through a valve. A first reactant forms a monolayer on the part to be coated, while the second reactant passes through a radical generator which partially decomposes or activates the second reactant into a gaseous radical before it impinges on the monolayer. This second reactant does not necessarily form a monolayer but is available to react with the monolayer. A pump removes the excess second reactant and reaction products completing the process cycle. The process cycle can be repeated to grow the desired thickness of film.Type: GrantFiled: August 16, 1996Date of Patent: June 29, 1999Inventor: Arthur Sherman
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Patent number: 5888845Abstract: A method of making a pressure sensor or acoustic transducer having high sensitivity and reduced size. A thin sensing diaphragm is produced by growing a single crystal, highly doped silicon layer on a substrate using a chemical vapor deposition process. The diaphragm is incorporated into a pressure sensor or acoustic transducer which detects pressure variations by a change in the capacitance of a capacitor which includes the diaphragm as a movable member. The thin diaphragm produces a highly sensitive device which can be fabricated in a smaller size than sensors or transducers having thicker diaphragms.Type: GrantFiled: May 2, 1996Date of Patent: March 30, 1999Assignee: National Semiconductor CorporationInventors: Rashid Bashir, Abul Kabir
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Patent number: 5871655Abstract: The present invention is an integral magnetic head suspension and method for making the same. The integral suspension, with or without the head, contains integrated conductive circuits that have multiple cross overs for noise reduction. The suspension is fabricated completely on silicon (Si) wafers using semiconductor processes. A N+ silicon layer is disposed over a P- silicon wafer. The N+ silicon layer and the P- silicon water are thermally oxidized to generate a bottom silicon oxide layer opposite the N+ layer side of the wafer and a top silicon oxide layer on the N+ side of the wafer, and to drive the N+ silicon into the P- silicon wafer. A layer of polysilicon is disposed over the silicon oxide layer on top of the N+ silicon layer. One or more pairs of conductive traces having multiple cross-overs are fabricated on the layer of polysilicon. Optimally, a magnetic head is simultaneously fabricated on the suspension.Type: GrantFiled: March 19, 1998Date of Patent: February 16, 1999Assignee: International Business Machines CorporationInventors: Edward Hin Pong Lee, Randall George Simmons