Abstract: Approaches provided herein are directed to intelligently boosting, in a power efficient manner, CPU frequency in response to a touch gesture event. In some approaches, for example, a governor of a processor receives an instruction hint (e.g., an interaction hint or a vertical synchronization (VSYNC) hint) from a power hardware abstraction layer (HAL), the instruction hint provided in response to at least one of: a scrolling touch gesture to a user interface, and an application launch touch gesture. In another embodiment, an instruction hint is received at the governor in response to a discrete touch gesture to the user interface. In each case, a clock frequency corresponding to the processor is modified to optimize performance and user experience, while maximizing energy conservation.

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

Abstract: A multi-core processor has: a plurality of processor cores; and a power management part managing power supplied to the plurality of processor cores. The power management part has a supplied electric energy determination part determining maximum supplied electric energy for each of the plurality of processor cores. The maximum supplied electric energy is an upper limit value of supplied electric energy which can be supplied to the processor core.

Abstract: Thermo-migration induced stress in power devices can be mitigated by deactivating a subset of power device components (e.g., transistors, etc.) when the power device experiences a high stress condition. Deactivating the subset of power device components serves to bifurcate the active area of the power switching device into smaller active regions, which advantageously changes the temperature gradients in the active area/regions. In some embodiments, a control circuit dynamically deactivates different subsets of power device components to shift the thermo-migration induced stress points to different portions of the active region over the lifetime of the power switching device.

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop.

Abstract: A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N?1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.

Abstract: The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: An information processing system includes a first server, a second server and an information processing apparatus, the information processing apparatus including a processor configured to manage a process of causing OS running on the first server to run on the second server, and the first server including a driver configured acquire an address of the physical memory area allocated for running Booting OS to boot the OS and a controller configured to notify the processor of the address of the physical memory area, wherein the processor causes the Booting OS to run at the address of the physical memory area of the first server or the second server, and causes the OS to run on the second server by transferring the OS to the second server from the first server.

Abstract: An information handling system includes an application processor that executes instructions of an intelligent energy management system that determines energy demand estimation based on component device utilization data from a group of client information handling systems. The information handling system includes a power policy engine that determines a timeseries power cost estimation based on the energy demand estimation, day and time of energy usage, and energy rate for the time and location.

Abstract: An image processing apparatus that operates in a first power state or a second power state in which power consumption is smaller than in the first power state includes a detection unit that includes regions in which an object is detected, an analysis unit configured to analyze results of detection obtained in the plurality of regions, wherein the analysis unit enters a power saving mode in the second power state, a control unit that causes the analysis unit to return from the power saving state in a case where an object has been detected in any of the plurality of regions included in the detection unit in the second power state, and a power control unit that, in a case where the analysis unit determines that an object has approached the image processing apparatus, shifts the image processing apparatus from the second power state to the first power state.

Abstract: A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.

Abstract: An apparatus includes a BLUETOOTH low energy (BLE) based emergency backup and recovery tool. The tool includes a backup power source that stores electric energy and outputs electric energy when a main power source is off. The tool includes a shared memory accessible by a processor and a BLE module. The shared memory stores information written by the processor, and operates using at least some of the electric energy output from the backup power source when the main power source is off. The tool includes the BLE module coupled to the backup power source. The BLE module operates using at least some of the electric energy output from the backup power source when the main power source is off, reads the information stored in the shared memory, and transmits the information to an external device through a wireless communication channel using a BLUETOOTH communication protocol.

Abstract: Systems and methods of power-safe control panel installation are provided. Some systems can include a control panel that includes a programmable processor and executable control software stored on a non-transitory computer readable medium, wherein the programmable processor and the executable control software can transmit a signal to selectively remove power from at least one portion of the control panel.

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

Abstract: A power excursion warning system includes a power system having a first slew rate. A powered component is coupled to the power system. The powered component voltage regulator has a second slew rate that is greater than the first slew rate. A powered component voltage regulator is coupled to the powered component and operable to convert a first voltage received from the power system to a second voltage that is supplied to the powered component. A power excursion warning device is coupled to the powered component voltage regulator and operable to receive a signal from the powered component voltage regulator that is associated with the second slew rate, determine that the signal indicates a power excursion that will result in the power system operating outside a predetermined range, and produce a warning signal indicative of the power excursion.

Abstract: An operation control device for an electronic apparatus is provided.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A method is used in managing disk drive power saving in data storage systems. Multiple data storage systems storage elements capable of operating in a power saving mode are identified and grouped into a RAID group. One or more logical units are created from the RAID group. The one or more logical units are exposed to a server. The one or more logical units are associated to an application at the server. Power saving settings are determined. A power saving mode based on the power saving settings is enabled.

Abstract: Provided is a manner of switching between the operating environment of a primary OS and the operating environment of a secondary OS. In certain embodiments, a HDD keeps a runtime image of the secondary OS generated in a system memory. A DMA space for allowing the secondary OS to operate is formed in a physical address space where a memory image of the primary OS is active. The runtime image of the secondary OS is transferred to the DMA space. The operation of the memory image of the primary OS is stopped and the runtime image of the secondary OS is executed in the DMA space. Before activating the memory image of the primary OS, the runtime image of the secondary OS is saved to the HDD again.