Abstract: A semiconductor memory is capable of executing a logical operation, which comprises at least one sense amplifier having a pair of inputs connected to a pair of bit lines; and a pair of output lines connected to the pair of bit lines, respectively. At least a pair of memory cells and a pair of dummy cells are connected to the pair of bit lines, respectively. Further, at least a pair of word lines are connected to the pair of memory cells, respectively, and a pair of dummy word lines connected to the pair of dummy cells, respectively. A word selecting circuit is connected to the pair of word lines and is capable of activating the pair of word lines at the same time. In addition, a dummy cell selecting circuit is connected to the pair of dummy word lines and adapted to alternatively activate the pair of dummy cells.

Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal.

Abstract: A field-programmable device contains a buffer (20) located between a pair of programmable circuits (14 and 16) along a column (10) connecting the circuits. The buffer provides increased current to the column portion connected to one of the circuits (16) without increasing the current supply requirements for the column portion connected to the other circuit (14). This permits the device to switch faster and/or to accommodate programmable circuits of large size. The buffer also enables the same select circuitry to be used in programming both circuits without causing a significant voltage between them during normal operation.

Abstract: A nonvolatile memory (programmable) comprises a plurality of logic memories, each of which is composed of a plurality of memory segments. Each of the memory segments is constituted of a first nonvolatile memory area capable of storing data of a predetermined bit number and a second nonvolatile memory area containing an identifier for the corresponding first nonvolatile memory area. Each of the logical memories is given one logical address, and when write operation is executed, a controller operates to access to the logical memory identified by the inputted logical address so as to erase in the accessed logical memory the memory segment having the identifier indicating that the data is stored, and to write the inputted data to the memory segment next to the erased memory segment.

Abstract: In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit.

Abstract: A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).

Abstract: A digital memory structured of interconnection substrates, input and output substrates and memory substrates affixed to a cooling insert.

Abstract: An EEPROM has two arrays which provide data in response to an address. The EEPROM can be programmed to function in one of two modes. The EEPROM can supply data from a selected one of the arrays or can simultaneously supply data from both arrays. In the mode in which data is supplied simultaneously from both arrays, the data from both arrays is coupled to a common data line where the data is sensed by a sense amplifier.

Abstract: An optical memory system for storage and retrieval of digital data using a source of writing light in the visible light range and a separate source of near infrared, polarized reading light. The writing light is amplitude modulated by a signal containing the digital data to be stored. Horizontal and vertical deflectors deflect the beams to scan horizontally and vertically in response to control signals. The scanning beams are focused to a focal point to impinge upon a stationary medium manufactured of a dry film having submicron electrically photosensitive particles embedded in a thermoplastic layer mounted on a substantially transparent electrically conductive substrate. The particles are insensitive to light at the reading light wavelength. The particles are initially uncharged and the film is sensitive to light after receiving an initial surface charge.

Abstract: A method and an apparatus for recording a digital information signal are disclosed in which a signal to be recorded is pulse-code-modulated (PCM) and the PCM signal is recorded on a recording medium by a rotary head as a slant tracks with no guard band between adjacent tracks and then reproduced therefrom. In this case, a tracking pilot signal is recorded on a part of each track independently of the PCM signal. The recording positions of the pilot signals on respective tracks are determined in such a manner that when succeeding three tracks are seen from the direction perpendicular to the tracing direction of the rotary head, they are not superimposed upon one another. Upon reproducing, when the record track is traced by the rotary head, the pilot signals from both tracks adjacent to the track to be traced are reproduced and a tracking signal is generated from the reproduced outputs whereby a playback rotary head traces the record track.