Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

Abstract: A semiconductor storage device includes: a semiconductor substrate; a plurality of circuit regions; and an element isolation region having a trench shape formed between the circuit regions. In the element isolation region including a thermal oxide film and a silicon oxide film, a sub-trench is formed in a bottom corner portion, and the thermal oxide film covers at least an inner wall of the sub-trench.

Abstract: The present invention addresses the problem of providing a photosensitive resin composition which exhibits good imidization rate even in cases where the photosensitive resin composition is fired at a temperature of 200° C. or less, while having high pattern processability, and a cured film of which exhibits high long-term reliability if used in an organic EL display device. In order to solve the above-described problem, a photosensitive resin composition according to the present invention contains (a) a polyimide precursor, (b) a phenolic compound having an electron-withdrawing group and (c) a photosensitive compound; and the polyimide precursor (a) has a residue which is derived from a diamine that has an ionization potential of less than 7.1 eV.

Abstract: An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

Abstract: A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.

Abstract: A light-emitting device with high emission efficiency and reliability is provided. The light-emitting device includes a fluorescent light-emitting layer and a phosphorescent light-emitting layer. A host material used in the fluorescent light-emitting layer has a function of converting triplet excitation energy into light emission and a guest material used in the fluorescent light-emitting layer emits fluorescence. The guest material has a molecular structure including a luminophore and a protecting group, and one molecule of the guest material includes five or more protecting groups. The introduction of the protecting groups into the molecule inhibits transfer of triplet excitation energy from the host material to the guest material by the Dexter mechanism. An alkyl group or a branched-chain alkyl group is used as the protecting group.

Abstract: A semiconductor device includes a semiconductor substrate on which a first insulation film is provided. A first conductive film is on the first insulation film. First electrode films are on the first conductive film and stacked. A charge accumulation member is between one of the first electrode films and the semiconductor member. The first conductive film includes a main body arranged below the first electrode films and an outer peripheral portion provided in an outer periphery of the main body to be apart from the main body. First and second slits are alternately provided in the outer peripheral portion, and extend along the outer periphery of the main body. The first and second slits are apart from each other as viewed in the stacking direction, and partly overlap each other as viewed in a first direction directed from the main body toward the outer peripheral portion.

Abstract: An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.

Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.

Abstract: A semiconductor memory device includes a first conductive layer, a semiconductor layer extending in a first direction and being opposed to the first conductive layer, and a gate insulating film disposed between the first conductive layer and the semiconductor layer. The first conductive layer includes a first region, a second region disposed between the first region and the gate insulating film, and a third region disposed between the first region and the first interlayer insulating layer. The first to the third regions contain a metal. The third region contains silicon (Si). The first region does not contain silicon (Si) or has a lower silicon (Si) content than a silicon (Si) content in the third region. The second region does not contain silicon (Si) or has a lower silicon (Si) content than the silicon (Si) content in the third region.

Abstract: A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer.

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Abstract: Methods and apparatus for enhancing simulated annealing with quantum fluctuations. In one aspect, a method includes obtaining an input state; performing simulated annealing on the input state with a temperature reduction schedule until a decrease in energy is below a first minimum value; terminating the simulated annealing in response to determining that the decrease in energy is below the first minimum level; outputting a first evolved state and first temperature value; reducing the temperature to a minimum temperature value; performing quantum annealing on the first evolved state with a transversal field increase schedule until a completion of a second event occurs; terminating the quantum annealing in response to determining that a completion of the second event has occurred; outputting a second evolved state as a subsequent input state for the simulated annealing, and determining that the completion of the first event has occurred.

Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.