Patents Examined by Amar Movva
  • Patent number: 11222828
    Abstract: The present invention provides an array substrate and a display panel. The array substrate includes a fan-out region, an array test region having multiple array test pads and multiple test switches, and a cell test region having multiple cell test pads and a dummy pad. A control end of each test switch is connected to the dummy pad, and the array test pads are connected to the first signal lines through the test switches. According to a high-level signal or a low-level signal received by the dummy pad, the test switch is turned on or off to conduct an array test or a cell test.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 11, 2022
    Inventor: Baoqin Fu
  • Patent number: 11217679
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Patent number: 11217621
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Patent number: 11217534
    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Ji Yong Park, Kyu Oh Lee
  • Patent number: 11205702
    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 21, 2021
    Assignee: Soitec
    Inventors: Christophe Figuet, Ludovic Ecarnot, Bich-Yen Nguyen, Walter Schwarzenbach, Daniel Delprat, Ionut Radu
  • Patent number: 11205717
    Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer
  • Patent number: 11203524
    Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jose Antonio Martinez
  • Patent number: 11195826
    Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 7, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Washington Lamar, Sagar Saxena, Chung C. Kuo, Sebastian Courtney, Sundar Chetlur
  • Patent number: 11183594
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
  • Patent number: 11183489
    Abstract: A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 23, 2021
    Assignee: AUDI AG
    Inventors: Andreas Apelsmeier, Johann Asam
  • Patent number: 11183439
    Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 23, 2021
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11177227
    Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Anokiwave, Inc.
    Inventors: Gaurav Menon, Jonathan P. Comeau, Nitin Jain
  • Patent number: 11177243
    Abstract: Micro light-emitting diode (LED) display fabrication and assembly are described. In an example, a micro-light emitting diode (LED) display panel includes a display backplane substrate having a plurality of metal bumps thereon. A plurality of LED pixel elements includes ones of LED pixel elements bonded to corresponding ones of the plurality of metal bumps of display backplane substrate. One or more of the plurality of LED pixel elements has a graphene layer thereon. The graphene layer is on a side of the one or more of the plurality of LED pixel elements opposite the side of the metal bumps.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi
  • Patent number: 11171303
    Abstract: The disclosure relates to the field of display technologies, and discloses a display panel and a method for fabricating the same, and the display panel includes: a base substrate, a pixel definition layer and a cathode layer arranged on one side of the base substrate successively, and a transparent electrically-conductive film arranged on the side of the cathode layer away from the base substrate, wherein the transparent electrically-conductive film is electrically connected with the cathode layer so that the transparent electrically-conductive film is in parallel to the cathode layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 9, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhiliang Jiang, Pan Zhao, Chao Kong
  • Patent number: 11164895
    Abstract: The present disclosure relates to an array substrate, a method for manufacturing the same, a display panel, and a display device. The array substrate includes: a gate metal layer, disposed on the substrate and the gate metal layer including a grounding wire located in the peripheral region; a gate insulating layer, at least covering the gate metal layer; and a conductive layer structure, disposed over the gate insulating layer and including an auxiliary grounding wire located in the peripheral region, wherein the auxiliary grounding wire is connected to the grounding wire. The present disclosure can prevent ESD more effectively.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 2, 2021
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xiaofang Gu, Xiaoye Ma, Xiping Wang
  • Patent number: 11165010
    Abstract: In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Peter Lewandowski, Jae-Woong Nah, Nicholas Torleiv Bronn
  • Patent number: 11158602
    Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 ?m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
  • Patent number: 11158592
    Abstract: Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Shibata, Atsushi Kurokawa
  • Patent number: 11138499
    Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Jack T. Kavalieros, Ian A. Young, Sasikanth Manipatruni, Ram Krishnamurthy, Uygar Avci, Gregory K. Chen, Amrita Mathuriya, Raghavan Kumar, Phil Knag, Huseyin Ekin Sumbul, Nazila Haratipour, Van H. Le
  • Patent number: 11133395
    Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng Hung, Kuan-Ting Liu, Jun-Nan Nian