Patents Examined by Amar Movva
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Patent number: 12046667Abstract: We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal.Type: GrantFiled: May 7, 2020Date of Patent: July 23, 2024Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Patent number: 12041776Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.Type: GrantFiled: July 26, 2023Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 12040386Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.Type: GrantFiled: December 19, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12033962Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.Type: GrantFiled: August 10, 2023Date of Patent: July 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
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Patent number: 12033061Abstract: A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.Type: GrantFiled: December 14, 2020Date of Patent: July 9, 2024Assignee: International Business Machines CorporationInventors: Chen Zhang, Jie Yang, Dexin Kong, Tenko Yamashita
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Patent number: 12033971Abstract: Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.Type: GrantFiled: September 29, 2023Date of Patent: July 9, 2024Assignee: Laird Technologies, Inc.Inventors: Vijayaraghavan Rajagopal, Eugene Anthony Pruss, Richard F. Hill
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Patent number: 12022658Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of theType: GrantFiled: July 20, 2023Date of Patent: June 25, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Kwangyoung Jung, Sangyoun Jo, Kohji Kanamori, Jeehoon Han
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Patent number: 12015065Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.Type: GrantFiled: July 25, 2023Date of Patent: June 18, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Katherine H. Chiang, Chung-Te Lin
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Patent number: 12010833Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.Type: GrantFiled: July 17, 2023Date of Patent: June 11, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
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Patent number: 12002706Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: GrantFiled: July 3, 2023Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Patent number: 11995388Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.Type: GrantFiled: May 15, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin
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Patent number: 11984380Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.Type: GrantFiled: July 8, 2021Date of Patent: May 14, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Masao Kondo, Kenji Sasaki, Shigeki Koya
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Patent number: 11978715Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.Type: GrantFiled: May 19, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Tsung Kuo, Hui-Chang Yu, Chih-Kung Huang, Wei-Teng Chang
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Patent number: 11963359Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 19, 2023Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: John D. Hopkins, Jordan D. Greenlee
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Patent number: 11953830Abstract: The present invention addresses the problem of providing a photosensitive resin composition which exhibits good imidization rate even in cases where the photosensitive resin composition is fired at a temperature of 200° C. or less, while having high pattern processability, and a cured film of which exhibits high long-term reliability if used in an organic EL display device. In order to solve the above-described problem, a photosensitive resin composition according to the present invention contains (a) a polyimide precursor, (b) a phenolic compound having an electron-withdrawing group and (c) a photosensitive compound; and the polyimide precursor (a) has a residue which is derived from a diamine that has an ionization potential of less than 7.1 eV.Type: GrantFiled: March 4, 2020Date of Patent: April 9, 2024Assignee: TORAY INDUSTRIES, INC.Inventors: Yusuke Komori, Takashi Sumi, Kazuto Miyoshi
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Patent number: 11955372Abstract: A semiconductor storage device includes: a semiconductor substrate; a plurality of circuit regions; and an element isolation region having a trench shape formed between the circuit regions. In the element isolation region including a thermal oxide film and a silicon oxide film, a sub-trench is formed in a bottom corner portion, and the thermal oxide film covers at least an inner wall of the sub-trench.Type: GrantFiled: August 20, 2021Date of Patent: April 9, 2024Assignee: KIOXIA CORPORATIONInventors: Takehiro Nakai, Mizuki Tamura, Yumiko Yamashita
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Patent number: 11955450Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.Type: GrantFiled: May 2, 2023Date of Patent: April 9, 2024Assignee: Infineon Technologies AGInventor: Olaf Hohlfeld
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Patent number: 11948908Abstract: An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.Type: GrantFiled: June 23, 2021Date of Patent: April 2, 2024Assignee: Japan Display Inc.Inventor: Kazuyuki Yamada
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Patent number: 11943918Abstract: A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.Type: GrantFiled: April 17, 2023Date of Patent: March 26, 2024Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Liang Han, Hai Ying Wang
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Patent number: 11943937Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.Type: GrantFiled: February 20, 2023Date of Patent: March 26, 2024Assignee: Zeno Semiconductor Inc.Inventors: Jin-Woo Han, Yuniarto Widjaja