Patents Examined by Amar Movva
  • Patent number: 12015065
    Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin
  • Patent number: 12010833
    Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 12002706
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Patent number: 11995388
    Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin
  • Patent number: 11984380
    Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 14, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Kenji Sasaki, Shigeki Koya
  • Patent number: 11978715
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tsung Kuo, Hui-Chang Yu, Chih-Kung Huang, Wei-Teng Chang
  • Patent number: 11963359
    Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Patent number: 11953830
    Abstract: The present invention addresses the problem of providing a photosensitive resin composition which exhibits good imidization rate even in cases where the photosensitive resin composition is fired at a temperature of 200° C. or less, while having high pattern processability, and a cured film of which exhibits high long-term reliability if used in an organic EL display device. In order to solve the above-described problem, a photosensitive resin composition according to the present invention contains (a) a polyimide precursor, (b) a phenolic compound having an electron-withdrawing group and (c) a photosensitive compound; and the polyimide precursor (a) has a residue which is derived from a diamine that has an ionization potential of less than 7.1 eV.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 9, 2024
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Yusuke Komori, Takashi Sumi, Kazuto Miyoshi
  • Patent number: 11955450
    Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: April 9, 2024
    Assignee: Infineon Technologies AG
    Inventor: Olaf Hohlfeld
  • Patent number: 11955372
    Abstract: A semiconductor storage device includes: a semiconductor substrate; a plurality of circuit regions; and an element isolation region having a trench shape formed between the circuit regions. In the element isolation region including a thermal oxide film and a silicon oxide film, a sub-trench is formed in a bottom corner portion, and the thermal oxide film covers at least an inner wall of the sub-trench.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: April 9, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Takehiro Nakai, Mizuki Tamura, Yumiko Yamashita
  • Patent number: 11948908
    Abstract: An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 2, 2024
    Assignee: Japan Display Inc.
    Inventor: Kazuyuki Yamada
  • Patent number: 11943918
    Abstract: A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: March 26, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Liang Han, Hai Ying Wang
  • Patent number: 11943937
    Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: March 26, 2024
    Assignee: Zeno Semiconductor Inc.
    Inventors: Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 11929365
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 12, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Shinya Umeki
  • Patent number: 11930645
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.
    Type: Grant
    Filed: March 5, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
  • Patent number: 11930653
    Abstract: A light-emitting device with high emission efficiency and reliability is provided. The light-emitting device includes a fluorescent light-emitting layer and a phosphorescent light-emitting layer. A host material used in the fluorescent light-emitting layer has a function of converting triplet excitation energy into light emission and a guest material used in the fluorescent light-emitting layer emits fluorescence. The guest material has a molecular structure including a luminophore and a protecting group, and one molecule of the guest material includes five or more protecting groups. The introduction of the protecting groups into the molecule inhibits transfer of triplet excitation energy from the host material to the guest material by the Dexter mechanism. An alkyl group or a branched-chain alkyl group is used as the protecting group.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Ishisone, Nobuharu Ohsawa, Satoshi Seo
  • Patent number: 11925029
    Abstract: A semiconductor device includes a semiconductor substrate on which a first insulation film is provided. A first conductive film is on the first insulation film. First electrode films are on the first conductive film and stacked. A charge accumulation member is between one of the first electrode films and the semiconductor member. The first conductive film includes a main body arranged below the first electrode films and an outer peripheral portion provided in an outer periphery of the main body to be apart from the main body. First and second slits are alternately provided in the outer peripheral portion, and extend along the outer periphery of the main body. The first and second slits are apart from each other as viewed in the stacking direction, and partly overlap each other as viewed in a first direction directed from the main body toward the outer peripheral portion.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Takamasa Ito, Hiroshi Matsumoto
  • Patent number: 11925025
    Abstract: An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 5, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Junichi Suzuki
  • Patent number: 11915928
    Abstract: A semiconductor memory device includes a first conductive layer, a semiconductor layer extending in a first direction and being opposed to the first conductive layer, and a gate insulating film disposed between the first conductive layer and the semiconductor layer. The first conductive layer includes a first region, a second region disposed between the first region and the gate insulating film, and a third region disposed between the first region and the first interlayer insulating layer. The first to the third regions contain a metal. The third region contains silicon (Si). The first region does not contain silicon (Si) or has a lower silicon (Si) content than a silicon (Si) content in the third region. The second region does not contain silicon (Si) or has a lower silicon (Si) content than the silicon (Si) content in the third region.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Masahiro Koike, Masao Shingu, Masaya Ichikawa
  • Patent number: 11916121
    Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Katherine H. Chiang, Chung-Te Lin