Abstract: A write pulse generator circuit which uses first and second flip-flop circuits adapted to provide output pulses to an exclusive OR gate to generate write pulses. The circuit includes apparatus for toggling the first flip-flop in response to a rising edge of a clock pulse, and apparatus for toggling the second flip-flop in response to a falling edge of the clock pulse. By utilizing opposite phase output signals from the flip-flops, tuning of the circuit for particular operating conditions and for particular processes is eliminated.