Abstract: A storage device, and a method for operating a storage device. In some embodiments, the storage device includes storage media, and the method includes: determining, by the storage device, that the storage device is in a first fault state from which recovery is possible by power cycling the storage device or by formatting the storage media; determining, by the storage device, that the storage device is in a second fault state from which partial recovery is possible by operating the storage device with reduced performance, with reduced capacity, or in a read-only mode; and operating the storage device with reduced performance, with reduced capacity, or in the read-only mode.

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

Abstract: A new approach is proposed to support systematic generation of a set of test cases/stimuli used to validate a multiprocessor system having a plurality of processors that supports memory coherence. A pair of two of the plurality of processors is first selected for testing one pair at a time, wherein a first of the pair is a requester requesting access to a cache associated with a second of the pair, which is a snooped requester. The test cases are automatically generated based on an algorithm-driven script, wherein the set of test cases includes an instruction set and all valid combinations of cache states of the processors. The instruction set is then executed by the pair of processors to validate memory coherence of the pair of processors. The above process is repeated so that each processor of the plurality of processors is included for memory coherence testing at least once.

Abstract: Mechanisms for reducing the impact of drive parameter writes on solid state drive (SSD) performance are provided, the methods including: saving one or more SSD drive parameters of an SSD to volatile memory of the SSD using an SSD controller; detecting a power-loss condition in the SSD; and copying the one or more SSD drive parameters from the volatile memory of the SSD to non-volatile memory of the SSD. In some embodiments, the SSD is a NAND SSD. In some embodiments, the one or more SSD drive parameters include one or more of: a drive health parameter, a drive internal statistic, drive thermal information, drive debug information, a number of host and non-volatile memory read and writes, media error handling data, temperature and throttle information, and firmware download information. In some embodiments, the volatile memory is one or more of: random-access memory and dynamic random-access memory.

Abstract: A method for locating a fault information is provided. The method includes: parsing error information of a target application to obtain version information and an error attribute of the target application; determining, based on the version information, a target mapping file corresponding to the error information; and determining a target location by utilizing the error attribute and the target mapping file, where the target location is used to determine a location of fault description content.

Abstract: A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a double data rate (DDR) fault isolation feature. The random number generator value may be compared against a predetermined parameter value and a determination may be made whether or not to extract and increment the counter based on a result of the comparison. A logic controller compares the counter value to a predetermined hotness threshold parameter and a flag is set based on an existence of an address match in local memory. Based on the results of the comparison, access to the DRAM is reduced.

Abstract: A data management system may support a configuration backup of a first backup system that manages backup procedures for data of a host environment that is separate from the first backup system. The data management system may transmit, to the first backup system, a request to generate the configuration backup that includes information for the one or more backup procedures managed by the first backup system. The data management system may cause the configuration backup to be stored in a separate storage location. In response to first backup system failure, the data management system may transmit, to a second backup system, a request to apply one or more configurations for the first backup system to the second backup system based on the stored configuration backup for the first backup system.

Abstract: A method for detecting a deadlock of a database management system and recovering from the deadlock includes: updating data stored in a first server and a second server; determining whether the database management system is in a deadlock state by comparing data of the first server with data of the second server; and recovering from the deadlock state by changing data of the first server or the second server so that the data of the first server and the second server are identical.

Abstract: Systems, apparatuses, methods, and computer program products for parallel processing of real-time data and accumulated data are provided. For example, a method provided herein may include determining that a computing device is affected by a fault during a first time period. The method may include receiving real-time data from the computing device via a network during a second time period. The method may include receiving accumulated data from the computing device via a network during the second time period. The method may include directing the real-time data to a real-time data processing unit and the accumulated data to an accumulated data processing unit. The method may include processing the real-time data with the real-time data processing unit and the accumulated data with the accumulated data processing unit. The method may include routing the real-time data and the accumulated data following the processing to one or more databases.

Abstract: Novel tools and techniques are provided for implementing intelligent alert automation (“IAA”). In various embodiments, IAA receives alert/event feeds from several different alerting and ticketing systems via input Redis queues, and uses a triage system to determine whether to process the alert/event or disregard it. If so, IAA may create a flow instance, assign a unique instance ID, and place the flow instance in one of a plurality of jobs queues based on alert/event type and/or or source. An abattoir system retrieves a flow instance from one of the jobs queues (in order of the queue's priority), and processes the next node or step in the flow instance. The flow instance is placed back into the jobs queue for subsequent processing by the same or different abattoir system until no additional nodes or steps remain in the flow, at which point the flow instance is considered complete.

Abstract: A system, method and apparatus of memory failure prediction through image analyses using an artificial neural network. A sequence of images indicative of progress of memory failures in a region of an integrated circuit die can be generated according to a physical layout of memory cells in the region. The artificial neural network can be trained to recognize graphical features in early images in the sequence and to predict, based on the recognized graphical features, memory failures shown in subsequent images in the sequence. A computing apparatus can use the artificial neural network to analyze an input image shown current memory failures in the region and to identify one or more memory cells in the region that are likely to have subsequent memory failures.

Abstract: Provided is a method for recovering data for artificial intelligence calculation, which is performed by one or more processors and which includes extracting, from a command queue, a descriptor associated with a target job, that is a job to be executed, of a plurality of jobs, executing at least one command associated with the extracted descriptor to execute artificial intelligence calculation associated with the target job, resetting the command queue if an error occurs while executing the artificial intelligence calculation, determining at least one descriptor to be recovered, based on tracking data associated with at least one job, and recovering the determined at least one descriptor to the reset command queue.

Abstract: A processing system for use in a vehicle comprises numerous simple processors, numerous parallel processors, an interface for connecting to a communication bus in the vehicle, and a monitoring device that is connected to the interface and each of the processors. The monitoring device is designed for redundant configuration of the simple processors and/or the parallel processors in relation to one another.

Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.

Abstract: A microcontroller unit includes at least one core, a plurality of safety fault management units, with each safety fault management unit including circuitry to detect one or more safety faults and to output an alarm signal in response to detection of one or more safety faults. The microcontroller further includes system control units operating in parallel to the at least one core. Each of the plurality of system control units can be coupled to at least one of the safety fault management units and can include hardware circuitry to generate and output a port emergency stop (PES) signal based on the alarm signals obtained from a safety fault management unit. The microcontroller includes port circuitries coupled to ports and to the system control units. The port circuitries can selectively cause a respectively connected port to enter a non-operational electronic state in response to receiving a PES signal.

Abstract: Provided are a flashing apparatus, a booting and recovery apparatus, and an electronic device, relating to the technical field of electronics. The flashing apparatus is applied to the electronic device. The electronic device includes a booting trigger module, a recovery trigger module, a booting control module and a recovery control module.

Abstract: Techniques are provided for persistent memory file system reconciliation. As part of the persistent memory file system reconciliation, high level file system metadata associated with a persistent memory file system of persistent memory is reconciled. Client access to the persistent memory file system is inaccessible until reconciliation of the high level file system metadata has completed. A first scanner is executed to traverse pages of the persistent memory in order to fix local inconsistencies associated with the pages. A local inconsistency of a first set of metadata or data of a page is fixed using a second set of metadata or data of the page. The first scanner is executed asynchronously in parallel with processing client I/O directed to the persistent memory file system.

Abstract: A hardware failure prediction and avoidance system executing on a unified endpoint management platform information handling system comprising a network interface device (NID) to receive failed operational telemetries for client devices including power and software analytics, and event viewer error logs, and an error associated with a hardware type, a processor to execute a classification supervised learning algorithm on the failed operational telemetries to determine that a hardware or software configuration will likely co-occur with a future error of the hardware type, identify the hardware or software configuration as problematic, the processor to identify the problematic system configuration in a current operational telemetry by correlating the current operational telemetry with a portion of the failed operational telemetries, and the NID to transmit a recommendation to the first client device to adjust the problematic system configuration in order to avoid occurrence of the error at the first client devic

Abstract: A method and apparatus with cosmic ray fault protection is included. A method includes obtaining cosmic ray information indicating at least one cosmic ray event, determining a soft error mitigation policy based on the cosmic ray information, accessing the soft error mitigation policy by a device, and based on the soft error mitigation policy, performing, by the device, a mitigation action that mitigates for soft errors related to the cosmic ray event.

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.