Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: A process of removing residue from an etched precision surface. In this process the etched precision surface is contacted with a composition which includes liquid or supercritical carbon dioxide and a fluoride-generating species.

Abstract: Methods and apparatuses for incorporating low contrast and high contrast interfaces in optical devices. In one embodiment an insulator is disposed proximate to a plurality of regions of a semiconductor including regions through which an optical beam is directed. High contrast interfaces are defined between the semiconductor and the insulator. Low contrast interfaces are defined between a doped region and the semiconductor. The optical beam is directed through the doped region from one of the plurality of semiconductor regions to another of the plurality of regions with relatively low loss. Optical coupling or evanescent coupling depending on an incident angle of the optical beam relative to the low contrast interface may occur through the doped region and low contrast interface.

Abstract: A method of manufacturing an LCD array substrate and LCD made by that method are disclosed. A plurality of gate lines, gate electrodes and gate extension lines are formed by depositing and patterning a first metallic material using a first mask. A first insulating layer is then formed. A plurality of data lines, source electrodes, drain electrodes, and capacitor electrodes are then formed by depositing and patterning suitable materials using a second mask. A passivation layer is then formed and patterned to create first and second contact holes using a third mask. The first contact holes expose the drain electrodes, the second contact holes expose the capacitor electrodes. A plurality of pixel electrodes are then formed by depositing and patterning a transparent conductive layer using a fourth mask. The pixel electrodes contact the drain electrodes through the first contact holes and contact the capacitor electrodes through the second contact holes.