Abstract: A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.

Abstract: Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.

Abstract: A semiconductor device has a clock signal generation circuit that generates a clock signal, and a processing circuit that operates in accordance with the clock signal. The semiconductor device can also include an external terminal and a power source terminal that is coupled to the processing circuit. The clock signal generation circuit changes the frequency of the clock signal to be generated in accordance with the voltage value of a current consumption signal supplied to the external terminal. Further, the voltage value of the current consumption signal is changed in accordance with current consumption flowing in the power source terminal. The clock signal generation circuit can change the frequency of the clock signal to be generated in accordance with a value of an analog signal supplied to the external terminal.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first circuit is coupled to the first terminal and the second terminal. The first circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and a delay setting. The delay setting corresponds to a delay between successive ON times of the first switch and the second switch. The second circuit is coupled to the first circuit. The second circuit is configured to monitor a first voltage on the first terminal and a second voltage on the second terminal, and to generate the delay setting based on at least the first voltage on the first terminal, or the second voltage on the second terminal.

Abstract: In one embodiment, a system includes a laser configured to generate a laser beam and a laser-aiming module configured to aim the laser beam to be at least in part incident on a remotely located, continuously moving solar cell. The system also includes a controller configured to receive a feedback signal indicating a position of the laser beam relative to the remotely located, continuously moving solar cell and instruct the laser-aiming module to adjust the aiming of the laser beam based on the feedback signal.

Abstract: The embodiments described herein include a transmitter that transmits a power transmission signal (e.g., radio frequency (RF) signal waves) to create a three-dimensional pocket of energy. At least one receiver can be connected to or integrated into electronic devices and receive power from the pocket of energy. A wireless power network may include a plurality of wireless power transmitters each with an embedded wireless power transmitter manager, including a wireless power manager application. The wireless power network may include a plurality of client devices with wireless power receivers. Wireless power receivers may include a power receiver application configured to communicate with the wireless power manager application. The wireless power manager application may include a device database where information about the wireless power network may be stored.

Abstract: Various on-die-precision-resistor arrays, and methods of making and calibrating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip and a precision resistor array on the semiconductor chip. A replica precision resistor array is on the semiconductor chip. The replica precision resistor array is configured to mimic the resistance behavior of the precision resistor array and has a characteristic resistance that is a function of temperature. The semiconductor chip is configured to calibrate the precision resistor array using the characterized resistance as a function of temperature, a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Abstract: A power transmitting apparatus that transmits power to a power receiving apparatus executes intermittent wireless transmission of power. The power transmitting apparatus operates according to one of a first power transmitting method including detecting a signal load-modulated by the power receiving apparatus using an ID in response to the transmitted power during the intermittent transmission and a second power transmitting method including transmitting the power having modulated the power according to an ID determined in advance so that the power receiving apparatus detects the ID determined in advance.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.

Abstract: An apparatus and method for continuously shifting the phase of an input signal includes a quadrature hybrid having an input/output port for receiving an input radio frequency (RF) signal and outputting a phase shifted RF signal. An analog shifting unit is connected to the quadrature hybrid for performing an intermediate phase shift on the input RF signal. An additional analog shifting unit is connected to an isolation port of the quadrature hybrid to receive an intermediate output signal based on the intermediate phase shift, and shifting a phase of the intermediate output signal to produce an intermediate input signal. The analog shifting unit performs a final phase shift of the intermediate input signal and the final phase shifted intermediate input signal is output, at the input/output port, as the phase shifted RF signal.

Abstract: A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.

Abstract: A reset circuit includes a detect circuit, a maintain circuit and an output circuit. The detect circuit and the maintain circuit are coupled to the output circuit, wherein the detect circuit is arranged to detect at least an input power provided to a loading, and make the output circuit output a reset signal when a voltage of the input power goes into an abnormal state, and the maintain circuit is arranged to stop the output circuit from outputting the reset signal when the loading is in a standby state. The reset circuit is applied within an electronic device.

Abstract: A semiconductor device includes: a transistor including a main terminal and a sense terminal; a main output electrode connected to the main terminal via a first wire; a sense output electrode connected to the sense terminal via a second wire; and a package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode, wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode.

Abstract: A direct current (DC) power supply system performs a method of delivering electrical energy by a synchronous buck voltage regulator (VR) coupled to an information handling resource of an information handling system by switching between a high side (HS) control switch and a low side (LS) synchronous switch to regulate a direct current (DC) output voltage (VOUT) generated from an input voltage (VIN). Inductor current (IMON) values of the voltage regulator are measured during LS synchronous switch ON state. IMON values of the voltage regulator are synthesized during HS power switch ON state. A complete inductor current signal is generated that combines the measured and synthesized IMON values.

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

Abstract: A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficiency of the charge pump when the multiplication ratio is at a first ratio, calculating a second efficiency of the charge pump when the multiplication ratio is a second ratio lesser than the first ratio, and based on the first efficiency and the second efficiency, determining at least one of a target output power and a target output voltage at which to change the multiplication ratio from the second ratio to the first ratio.

Abstract: This disclosure provides systems, methods and apparatus for implementing a non-blocking switch matrix. In one aspect, a switch matrix can include an arrangement of C-switches. Each of the C-switches can be configured to switch between two positions to couple between different channels. The C-switches can be arranged in the switch matrix as to provide non-blocking functionality such that each of the inputs of the switch matrix is routed to an output of the switch matrix in any combination of the configurations of the C-switches.

Abstract: A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

Abstract: A technique relates to a microwave switch. A first nondegenerate device includes a first port and a second port. A second nondegenerate device includes another first port and another second port, the second port being coupled to the another second port, where the first nondegenerate device and the second nondegenerate device are configured to receive a phase difference in microwave drives. A first input/output port is coupled to the first port and the another first port. A second input/output port is coupled to the first port and the another first port, where communication between the first input/output port and the second input/output port is based on the phase difference.