Abstract: The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer (2) on a substrate material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein the adhesion of the pressure-sensitive adhesive layer (2) to the die-bonding adhesive layer (3), as determined under the conditions of a peel angle of 15° and a peel point moving rate of 2.5 mm/sec. at 23° C., is different between a region (2a) corresponding to a work attachment region (3a) and a region (2b) corresponding to a part or the whole of the other region (3b), in the die-bonding adhesive layer (3), and satisfies the following relationship: adhesion of the pressure-sensitive adhesive layer (2a)<adhesion of the pressure-sensitive adhesive layer (2b), and the adhesion of the pressure-sensitive adhesive layer (2a) to the die-bonding adhesive layer (3) is not higher than 2.3 N/25 mm.

Abstract: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates and flex films through various manufacturing processes. The flexible substrate is bonded to a rigid carrier. The carrier is placed into a specialized fixture comprising a bottom plate and a top plate. The bottom plate with raised regions is created that allows the windowed region of the flex film to be pressed flat. After aligning the top plate, the bottom plate, and the middle structure, the plates are pressed together causing the raised regions to push the flex film substrate upward and around the carrier.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) in which both a base resistance and a base-collector parasitic capacitance are decreased. The HBT has a collector (C) 18, a base (B) 20 and an emitter (E) 26. The collector comprises an outer collector region and an inner collector region, a thickness of the outer collector region is greater than that of the inner region. The base comprises an intrinsic region and an extrinsic region on the outer collector region, while the intrinsic base disposed on the inner collector region. The emitter is disposed on both the intrinsic base and the extrinsic base, and has a band gap energy greater than that of the base.

Abstract: Process exhaust gas is sampled, and the components of the process exhaust gas are analyzed by a Fourier-transform infrared spectroscope (FT-IR) (26). The analysis result is compared with a reference analysis result obtained from an analysis of process exhaust gas generated in an operation performed under reference process conditions. If the amount of a gas component changes to an amount that is outside a predetermined range set around a reference value obtained from the reference analysis result, a signal indicating a process error is outputted. Instead of the output of the signal indicating a process error, the process conditions can be automatically adjusted.

Abstract: The present invention is directed to an automated method of controlling critical dimensions of features by controlling the stepper exposure dose, and a system for accomplishing same. In one embodiment, the method comprises measuring a critical dimension (FICD) of a plurality of features formed in a process layer, and providing the measured critical dimensions of the features to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer. In another embodiment, the method comprises measuring a critical dimension (DICD) of a plurality of features formed in a patterned layer of photoresist, providing the measured critical dimensions of the features in the patterned layer of photoresist to a controller that determines, based upon the measured critical dimensions, an exposure dose of an exposure process to be performed on at least one subsequently processed wafer.

Abstract: A method of determining the accuracy error in scanning signals of a semiconductor line width metrology device comprises the steps of creating a frequency signature template of a patterned feature formed on a semiconductor layer with a line width metrology measurement device that is in nominal operating condition. Another patterned feature similar to the first patterned feature is scanned and the waveform signal is generated of the line width patterned feature. The waveform signal is processed and converted into a frequency signature which is compared with the frequency signature template.

Abstract: A wafer mapping method and apparatus for automatically determining the location and orientation of workpieces within a workpiece processing tool. An illumination device is provided which directs light toward the edges of the workpieces and a vision system is utilized to receive and process the images obtained from the light which is reflected off the edges of the workpieces.

Abstract: A method for determining a crack limit of a target film deposited on a wafer in production after a post annealing procedure is disclosed. The crack limit is determined by adopting and adjusting the thermal shrinkage rates of a plurality of target films deposited on bare wafers and annealed. The test results on bare wafers can be applied to the production wafers to prevent from film cracking and/or inspect instrumental conditions.

Abstract: The present invention relates to a method for actually measuring misalignment of a via. According to the invention, a via is formed by etching an inter metal dielectric (IMD) layer using a photoresist with a via pattern as a mask so that via pattern can be accurately transferred to the inter metal dielectric layer. Then a patterned metal interconnection line underlying the inter metal dielectric layer is etched using the patterned inter metal dielectric layer as a mask and followed by a process of stripping the inter metal dielectric layer. After that, an actual misalignment can be detected by measuring relative distance between the patterned metal interconnection line and the via thereon through Scanning Electron Microscopy (SEM), by which overlay specifications for OSI instrument can be verified and adjusted.