Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.