Abstract: Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a design layout. The router (1) partitions the region into a first set of sub-regions, and (2) for each particular net, identifies a route that traverses a set of the first-set sub-regions. In some embodiments, the invention's method partitions the first set of sub-regions into a second set of smaller sub-regions. It then identifies a plurality of propagation possibilities for propagating each route into the second set of smaller sub-regions of the first set sub-regions. The method next formulates a linear-programming (“LP”) problem based on the identified propagation possibilities. The method then solves the LP problem.

Abstract: A photomask designing method and apparatus, a computer readable storing medium, a photomask, a photoresist, a photosensitive resin, a base plate, a microlens, and an optical element. In the method, even though a desired depth of a photoresist pattern and a type of the photoresist are changed, the photomask can be easily designed. In a method of designing a photomask in which intensity of light radiated onto the photoresist is controlled with a fine pattern, that is, a congregation of fine areas respectively having predetermined light transmission factor, the resist sensitivity curve showing resist depth for the exposing amount of the employed photoresist and fine areas data corresponding to plural light transmission factors per predetermined halftone are previously set, and then, the depth of the resist respectively set per each of the fine areas is converted to the light exposing amount by use of the resist sensitivity curve.

Abstract: A method and system for power node current waveform modeling provides improved accuracy for logic gate and functional block power node current models in computer-based verification and design tools. An output voltage waveform is generated, with each point a linear function of a set of input values corresponding to times at which the output voltage reaches predetermined fractions of the supply voltage. A set of coefficients is used for each point, as each output voltage has a different linear dependency on the input values. The output voltage waveform model is differentiated and multiplied by an effective load capacitance to determine an output current waveform. The method and system retain compatibility with existing software by using input values already present in the digital simulation models (e.g., delay times) that yield a subset of output voltage points. The coefficients of the model are predetermined for a circuit from principle components analysis.

Abstract: A reproduction method and system supports rapid convergence of a genetic optimization process. Mating, mutation, or both may be combined with biased parent selection during each mating season.

Abstract: Disclosed herein are swizzling techniques that may provide capacitive and inductive noise cancellation on a set of signal lines. Positive noise due to a capacitive coupling between attacker signal lines and near victim signal lines is, in part, cancelled by negative noise due to inductive coupling between the attacker signal lines and a far victim signal line. Repeatable swizzling patterns are set forth to transpose near victim signal lines and far victim signal lines in subsequent segments to facilitate the capacitive and inductive cancellation. The signal lines are optionally reordered by a final swizzling to restore the set's original ordering.

Abstract: Some embodiments provide a method of producing sub-optimal routes for a net having a set of pins in a region of an integrated-circuit (“IC”) layout. In some embodiments, such a method is used for a router that partitions the region into a plurality of sub-regions. This method initially identifies a first set of sub-regions that contain the net's pins. It then obtains a second set of sub-regions by adding a third set of sub-regions to the first set of sub-regions. Each sub-region in the third set does not contain any pins of the net. For the second set of sub-regions, the method then identifies a first set of routes, where each route traverses the sub-regions in the second set.

Abstract: A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to assign a shield potential. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A method and apparatus are described for allowing multiple users to simultaneously edit a design while being able to view edits to the entire design. A design (such as for a printed circuit board) having a plurality of exclusive areas is displayed to a plurality of users. A first user checks out a corresponding section of the design, and edits the design. A second user checks out a corresponding section of the design, and edits the design simultaneously with the first user editing the design.

Abstract: From a circuit diagram, an electrically connected circuit diagram network is selected. From a layout representing the circuit diagram, an electrically connected layout network is selected that represents the circuit diagram network. A first electrical terminal connection of a first component is selected that connects the first component with the circuit diagram network or with the layout network. A second electrical terminal connection of a second component is selected that connects the component with the circuit diagram network or with the layout network. A first electrical moment is calculated for the transmission path of the layout. A second moment of the corresponding transmission path of the circuit diagram is calculated. A relationship between the first moment and the second moment is predetermined. A value of a resistor or a value of the capacitor of the circuit diagram is now modified in such a way that the relationship is satisfied.

Abstract: A method and a system for using a graphics user interface for programming a microcontroller. The microcontroller design system includes a device editor system with integrated datasheet information and having three independent, but integrated workspaces to provide a programmer an organized way of displaying device editor information. The three workspaces include a user module selection workspace, a user module placement workspace and a user module pin out workspace for allowing the programmer to select desired function components for a target microcontroller device. The user module selection workspace allows the programmer to select desired components from a list of user modules and the placement workspace allows user modules to be placed in allowable hardware resources. The user module pin out workspace provides the programmer with the means to retrieve pin out information on the selected user modules that constitute the desired target microcontroller device design.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: A method of debugging an IKOS model. The method includes mapping information contained in either a .pin or .lde file or both into corresponding files which are more user-friendly, readable and editable. Preferably, a .v file which is readable to create a schematic view of the cell is also created and the schematic view can be viewed and analyzed. Then, the one or more user-friendly files which have been created can be read and edited, and the .pin and/or the .lde file is re-created. Then, a tool is used to analyze the .pin and .lde files again and determine whether there is a functional or timing failure.

Abstract: A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.

Abstract: An unused logic portion of a device is identified, where the unused logic portion of the device is part of a metal definable logic portion of the device. The unused logic portion is specified to be used as a bypass capacitor between a first and second power node.

Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a first set of routes based on a first wiring model and a second set of routes based on a second wiring model. Each identified set of routes traverses the particular set of potential sub-regions. The method then stores the identified routes.

Abstract: A method for determining device yield of a semiconductor device design, comprises determining statistics of at least one device parameter from at least two device layer patterns; and calculating device yield from the statistics. At least one of the device layer patterns is neither a diffusion layer pattern nor a gate poly layer pattern.

Abstract: A method is disclosed to integrate the creation of a milling path into printed circuit board (PCB) design. The method includes creating keepout regions based on a PCB outline and critical components components placed on the PCB design, calculating support tabs based on the created keepout regions, and then placing the support tabs along the border as calculated. A milling machine may then mill out the support tabs as designed without suffering the potentially undetectable defects in the milling process.

Abstract: An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.