Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11 ) to a source voltage (Vs) having a higher potential than the, control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.