Abstract: A bipolar transistor and method of fabricating the same is disclosed. Particularly, a bipolar transistor may have an emitter and a collector diffusion layer in the sidewalls and the bottom of a device isolation trench. A method includes the steps of: forming a device isolation trench in a substrate; forming a photoresist pattern and implanting ions into the sidewalls and the bottom of the trench to form an emitter and a collector; removing the photoresist pattern; and filling the trench with an insulation layer to form the device isolation structure. Accordingly, the transistor and method can minimize device area by forming the diffusion layer of an emitter and a collector in the sidewalls and the bottom of the trench, and can provide a deep impurity diffusion layer without a high temperature diffusion process. In addition, the transistor and method can provide both a high amplification factor and a high current driving force.

Abstract: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

Abstract: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

Abstract: A solid-state image pickup apparatus with little or no difference in the dark currents between adjacent photoelectric conversion elements and providing a high sensitivity and a low dark current even in a high-speed readout operation. A well 302 is formed on a wafer 301, and semiconductor layers 101a, 101b are formed in the well to constitute photodiodes. A well contact 306 is formed between the semiconductor layers 101a, 101b. Element isolation regions 303b, 303a are provided between the well contact and the semiconductor layers, and channel stop layers 307b, 307a are provided under the element isolation regions 303b, 303a. A conductive layer 304 is provided on the element isolation region 303b, and a side wall 308 is provided on a side face of the conductive layer 304. A distance a between an end of the element isolation region 303b and the conductive layer 304, a width b of the side wall 308 and a device isolation width c satisfy a relation c>a?b.

Abstract: A light-emitting device has a light-emitting portion having a light-emitting element; a heat dissipation base on which is mounted the light-emitting portion and which is exposed outwardly for dissipating heat produced by the light-emitting portion; a power feeding portion for feeding power to the light-emitting portion; and a sealing portion formed of a glass material being integral with the heat dissipation base for insulating the power feeding portion from the heat dissipation base.

Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.

Abstract: A solid-state imager is disclosed wherein isolation regions (4) are covered with power supply lines (8), a light-transmitting lens film (24) whose surface forms continuous convex portions above the isolation regions (4) convex towards channel regions (5) is provided, and a light-transmitting material having a refractive index lower than that of the lens film (24) is provided over the lens film (24).

Abstract: A sensor is provided, which includes a substrate, an insulating layer formed on the substrate, a semiconductor formed on the insulating layer, an ohmic contact formed on the semiconductor, a sensor input electrode and a sensor output electrode formed on the ohmic contact, and a passivation layer formed on the sensor input electrode and the sensor output electrode. A sensor control electrode may also be formed between the substrate and the insulating layer. A thin film transistor array panel including the sensor and a liquid crystal display panel including the sensor are further provided.

Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

Abstract: Disclosed is a method for forming a storage node contact of a semiconductor device. In such a method, there is provided a substrate formed with gates and source/drain regions. A landing plug poly is formed between the gates, and an insulating interlayer is formed over the entire surface of the substrate including the landing plug poly and the gates. The insulating interlayer is then etched to form a storage node contact hole exposing the landing plug poly. Thereafter, the landing plug poly exposed through the storage node contact hole is removed. Finally, a polysilicon film is filled up within a vacant portion from which the landing plug poly is removed and the storage node contact hole above the vacant portion.

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract: A method of fabricating a nonvolatile memory using quantum dots is disclosed. An example method sequentially forms a first insulation layer and a second insulation layer on a substrate where a predetermined device is formed. The example method also forms a hard mask by etching the second insulation layer, deposits silicon on the substrate where the hard mask is formed, forms quantum dots by etching the silicon through an etchback process, removes the hard mask, forms a third insulation layer on the substrate where the quantum dots are formed, and deposits a conductive layer on the third insulation and patterning it to form a gate.

Abstract: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad electrode. This etching is performed under an etching condition such that an opening diameter of the via hole at its bottom is larger than a width of the pad electrode. Next, a second insulation film is formed on the back surface of the semiconductor substrate including in the via hole 16, exposing the pad electrode at the bottom of the via hole. Next, a penetrating electrode and a wiring layer are formed, being electrically connected with the pad electrode exposed at the bottom of the via hole 16. Furthermore, a protection layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated in semiconductor dies by dicing.

Abstract: An impedance matching apparatus 3 calculates a forward wave voltage Vfo and a reflected wave voltage Vro at an output terminal 3b, based on a forward wave voltage Vfi and a reflected wave voltage Vri at an input terminal 3a, on information on variable values of variable capacitors VC1, VC2 acquired in advance through measurement, and on a T parameter of the impedance matching apparatus 3 corresponding to the information on the variable values of variable capacitors VC1, VC2. The impedance matching apparatus 3 calculates an input reflection coefficient ?i at the input terminal 3a corresponding to the information on the variable values of the variable capacitors VC1, VC2, based on the forward wave voltage Vfo, the reflected wave voltage Vro and the T parameter.

Abstract: A method, apparatus, and a localized in-line cable filter system are provided for implementing electromagnetic cable noise suppression. The localized in-line cable filter system includes at least one electromagnetic interference (EMI) filter element connected between a cable and a current return path. An insulation displacement terminal connects the EMI filter element to the cable. The EMI filter element and current return path provide a low impedance connection toward a source.

Abstract: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the creation of a new class of solid state chemical sensors. Detection of the following chemical species was established: hydrogen, deuterium, carbon monoxide, molecular oxygen. The detector (1b) consists of a Schottky diode between an Si layer and an ultrathin metal layer with zero force electrical contacts.

Abstract: A film bulk acoustic resonator includes a first electrode, a piezoelectric film disposed on the first electrode, a second electrode disposed on the piezoelectric film or disposed above the piezoelectric film, and an additional film disposed on and abutting the piezoelectric film. The additional film has at least one pair of opposite sides which are non-parallel with each other. The additional film includes a plurality of stripe-shaped openings.

Abstract: A manufacturing method of a semiconductor device disclosed herein comprises: forming a first protrusion; forming a second protrusion which is higher than the first protrusion; forming a first sidewall on a side surface of the second protrusion; forming a first film so that a surface of the first film is located lower than the second protrusion; forming a mask on a side surface of the first sidewall on a side surface of the second protrusion which protrudes from the surface of the first film; and etching the first film with the mask so as to form a second sidewall on the side surface of the first sidewall on the side surface of the second protrusion but not to form the second sidewall on a side surface of the first protrusion, the second sidewall being formed of the mask and the first film.

Abstract: An impedance matching apparatus 3 calculates a forward wave voltage Vfo and a reflected wave voltage Vro at an output terminal 3b, based on a forward wave voltage Vfi and a reflected wave voltage Vri at an input terminal 3a, on information on variable values of variable capacitors VC1, VC2 acquired in advance through measurement, and on a T parameter of the impedance matching apparatus 3 corresponding to the information on the variable values of variable capacitors VC1, VC2. The impedance matching apparatus 3 calculates an input reflection coefficient ?i at the input terminal 3a corresponding to the information on the variable values of the variable capacitors VC1, VC2, based on the forward wave voltage Vfo, the reflected wave voltage Vro and the T parameter.