Abstract: Semiconductor charge devices are defined to effect a serial-to-parallel conversion of analogue signal information. In one aspect of the invention, a digital signal is extracted from an analogue noise environment by a shift register correlator comprising a bucket-bridge configuration of field-effect transistors in combination with gating field-effect transistors which are effective to weight the amplitude of the data in corresponding bits of the shift register. The gates of the gating transistors are selectively connected to diffused regions of transistors of the bucket-brigade delay line to effect parallel tapped outputs therefrom. The weighted signals from the gating transistors are summed at a common terminal to form the auto-correlated output.

Abstract: Low resistance substrate contacts extending through the source region of an insulated gate field effect transistor (IGFET) will reduce parasitic bipolar effects in an integrated circuit. Such low resistance contacts may be made by diffusing impurities of a type opposite to the conductivity type of the source region through spaced areas of the source region thereby to provide low resistance paths between all points in the source and the underlying substrate. The low resistance contacts prevent large voltage drops in the substrate underlying the source thereby preventing "latch-up" of the parasitic devices formed during the manufacture of the integrated circuit.

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Abstract: The on-to-off switching time of a junction transistor is reduced by forward connecting a recombination layer diode between the base and collector of the transistor. Preferably, the diode comprises a semiconductor abrupt junction of the type having a relatively heavily doped region of first conductivity type, a relatively lightly doped region of opposite conductivity type, and immediately adjacent the effective junction, a thin "recombination layer" of a carrier recombination-generation type material with a dopant concentration intermediate that of the two junction regions. Such a diode exhibits very low forward turn-on voltage and fast forward and reverse recovery times. The diode functions to bypass base-collector toward current of the transistor so as to reduce excess stored charge at the transistor collector-base junction, thereby effectively eliminating the storage delay time typically associated with junction transistor turn-off.

Abstract: A precision sensistor structure is disclosed for use in a monolithic integrated circuit.

Abstract: A depletion mode load device structure is disclosed which improved upon the existing Weinberger layout technique, as applied to enhancement mode/depletion mode circuitry. The structure of an FET, self biased load device includes a single metallized vertical line performing three functions: a source contact for the FET device, the gate electrode for the FET device, and the output line for the circuit for which the device serves as the load. Use of this structure results in an increased horizontal circuit packing density, which is particularly useful in the decoder circuits for a programmed logic array.

Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction.

Abstract: Methods for storing and transferring electrical charges between adjacently spaced storage regions in semiconductor substrate are disclosed. In one embodiment, a plurality of adjacently spaced conductor members are insulatingly disposed over a major surface of a semiconductor substrate. Each storage region is separated from each other storage region by an electrical barrier region underlying the spacing between the adjacent conductor members. These barrier regions are controllably lowered by an electrode interposed between adjacent conductor members. Electrical charges stored in one storage region are transferred to an adjacent storage region by applying a voltage signal to the interposed electrode to lower the barrier region between the adjacent storage regions. Direction of charge transfer is controlled by the relative surface potentials of the adjacent storage regions and the magnitude of transfer is controlled by the height of the barrier region when lowered.

Abstract: Coiled incandescible filament which principally comprises tantalum carbide has coiled end portions thereof overfitting relatively thick tantalum carbide members, with the inner surfaces of the overfitting coils welded to the relatively thick members. Electrical connection and support for the filament is made to the relatively thick, overfitted members, rather than the fine, brittle filament. In order to effect the weld between the overfitting coils and the relatively thick members, the coils and relatively thick members are first overfitted as metals and then carbided, with diffusion welds therebetween formed during the carbiding process.

Abstract: A fusing technique whereby a fuse is fabricated upon a substrate by integrated circuit techniques. Three or more layers of chemically dissimilar metals are depositedupon the region where the fuse is to be formed. The top layers are then etched away from the region where the fusible link is to be formed leaving the lower two layers, the top one of which forms the actual fusible link. The lower layer is then etched away leaving the fusible link suspended from the underlying substrate. The current necessary to cause such a fuse to blow is consistent from fuse to fuse since the physical dimensions of the fusible link can accurately be controlled with the integrated circuit techniques used and, since the fusible link is not in contact with the substrate, the rate at which heat is conducted away from the fusible link cannot vary from fuse to fuse.

Abstract: A conventional construction thyristor is modified to remove the short from the shorted emitter which is then led out to a separate pin for external connection. This enables the use of a simpler zero voltage switching control circuit.

Abstract: A high repetition rate injection laser modulator wherein a DC bias voltage is applied across a serially connected forwardly-poled-injection laser and carrier-injected avalanche device. The carrier-injected avalanche device generates a current pulse in response to additional carriers injected into the device by a trigger pulse applied across the control junction of the avalanche device. An offset bias is provided across the control junction to remove built-up charges at the junction interface to provide for high repetition rate operation. The current pulse is of sufficient magnitude to effect pumping of the injection laser, the injection laser thus emitting a corresponding pulse of coherent light.

Abstract: A low pressure transducer and methods of fabricating the same employ piezoresistive bridges deposited on or diffused within a wafer of n-type silicon, the wafer is secured to a glass sheet and is then bonded to a silicon diaphragm of a relatively large size and fabricated from a distinct piece of silicon of non-critical electrical characteristics. Methods for producing a plurality of such devices by using compatible processing steps are also provided.

Abstract: A plastic housing structure, for a semiconductor component or integrated circuit, employing a metallic heat conducting member forming a base plate of the housing, the conductor members for electrical connection of the semiconductor component extending from the latter to the base plate and insulated therefrom by a plastic film, with the housing being suitable for reception of semiconductor components of integrated circuits and mounting thereof into conductor boards or layer circuits.

Abstract: A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

Abstract: A semiconductor device has a conductive layer for wiring which is made of an Al alloy containing Mn in an amount greater than 1 percent by weight and below 6 percent by weight. The semiconductor device has excellent corrosion resistance, and has a high reliability.

Abstract: This describes an integrated semiconductor structure having an epitaxial semiconductor layer, divided into regions by isolation zones and containing active and passive semiconductor devices, of a first conductivity type on a substrate of the opposite second conductivity type. A reference potential and first and second supply voltages are applied to the structure. An additional isolated transistor, in accordance with this invention prevents an unlimited current flow, via the chip isolation junction, from one voltage supply to the other when the power-on sequence for both voltages is undefined. The base of this additional transistor is connected to one of the voltages via an integrated resistor while the other voltage is connected to the emitter and the collector is connected to the substrate via the isolation zone. Thus, the isolation junction can never become forward biased.

Abstract: A diode package comprising a compressible dielectric member having an aperture extending through its two major opposite surfaces. An electrically conductive lid is attached on one of the major surfaces of the dielectric member and an electrically conductive base is attached on the other surface. A semiconductor diode having two terminals oppositely situated is soldered with one diode terminal to the base within the aperture of the dielectric member. The lid is further soldered to the other diode terminal subsequent to the compressible dielectric member being compressed an amount sufficient for the lid to make an electrical connection to the other diode terminal.

Abstract: Disclosed is a porous anode electrolytic capacitor and casing therefor. The casing is made of nickel and has a contoured inner surface with a thin layer of silver plating thereon which follows the contour thereof. Adhered to the silver plating is a porous layer of particles of a platinum group metal which enhances the cathode surface area of the capacitor. Also disclosed is a timing capacitor including the casing. The capacitor is useful at temperatures up to 125.degree. C.

Abstract: A solid-state charge-coupled photoconductor for image scanning including a p-type substrate having a silicon dioxide layer on the surface thereof with the exception of one or more areas in which an n+ diffusion area is located. A polysilicon gate is located over the silicon dioxide layer and a second silicon dioxide layer is located over the polysilicon layer and the n+ diffusion area except for a portion where a first aluminum contact window is provided which extends through the second silicon dioxide layer to the surface of the n+ diffusion area and where a second aluminum contact window extends through the second polysilicon gate to the surface of the polysilicon gate. The photosensitivity of the device is electronically controlled due to the relatively small n+ layer which is reversed biased with respect to the larger gate area.