Abstract: The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness of the polishing stop points material being larger than hardness of the surface material. Therefore, the present method can achieve super flat polishing surface without removing polishing stop points.

Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.

Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Abstract: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.

Abstract: An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor; and an interconnect layer which forms an output signal wire which shields the floating diffusion interconnect layer.

Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.

Abstract: The power semiconductor module (1) comprises several semiconductor components (6, 7, 8), located on a substrate (2). The aim of the invention is to prevent a reduction in the pressure of the substrate against a cooling surface and the resulting loss of cooling arising from deformations. Said aim is achieved, whereby the substrate (2) comprises several substrate regions (3, 4, 5), with one or several connection regions (31, 32), located between substrate regions (3, 4, 5), by means of which the substrate regions (3, 4, 5) are connected such as to move relative to each other.

Abstract: An organic memory device having a memory active region formed by an embossing structure. This invention provides an organic memory device including a substrate, a first electrode formed on the substrate, an organic memory layer formed on the first electrode, a second electrode formed on the organic memory layer and an embossing structure provided at the organic memory layer to form a memory active region.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.

Abstract: A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.

Abstract: A solid state imaging device, includes: a sensor cell array having a plurality of sensor cells arranged in a matrix on a substrate, each sensor cell including: a photoelectric transducer provided in the substrate and generating photo-generated electric charges according to an incident light; a transfer gate formed on the substrate with a gate insulating layer therebetween; a charge retention region formed under the gate insulating layer and storing the photo-generated electric charges that are transferred from the photoelectric transducer by applying a predetermined potential to the transfer gate; a buried layer formed between the charge retention region and the gate insulating layer; and a floating diffusion storing the photo-generated electric charges that are transferred from the charge retention region by applying a predetermined potential to the transfer gate.

Abstract: A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.

Abstract: A discrete stress isolation apparatus for a Micro Electro-Mechanical System (MEMS) inertial sensor device having a mechanism die and a package. A capacitive device mechanism is formed in a substrate layer positioned between the mechanism die and package substrate. A discrete stress isolation structure is formed in the same substrate layer with but physically separated from the capacitive device mechanism. The discrete stress isolation structure is interposed between the mechanism die and the package substrate and provides the mechanical and electrical attachment therebetween.

Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.

Abstract: A semiconductor device is disclosed. The device includes: oppositely disposed plural electrodes; a semiconductor molecule disposed such that one end part thereof binds to a surface of the electrode in each of the opposing electrodes; and a conductor for electrically connecting at least a part of the other end part of the semiconductor molecule disposed in one electrode of the opposing electrodes to at least a part of the other end part of the semiconductor molecule disposed in the other electrode of the opposing electrodes. The conductivity between the opposing electrodes is substantially determined by the conductivity of the semiconductor molecule electrically connected to the conductor between the opposing electrodes in the semiconductor molecules.

Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J1, J2 with the channel. At least transistors FET1,1, FET1,2 of the array are differentiated by a different conducting material (m1, m2) of the source electrode S and/or drain electrode D.

Abstract: In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series with the first bond wire. A third bond wire is disposed on the semiconductor substrate so that a mutual inductance between the second bond wire and the third bond wire at least partially cancels a mutual inductance between the first bond wire and the second bond wire.