Patents Examined by Andrew Roberts
  • Patent number: 5610832
    Abstract: Method and apparatus for providing multiple connection modes in a CAD tool or other computer program for integrated circuit design. The apparatus includes a graphical editor for entering and modifying, in memory, circuit elements of an integrated circuit layout. Within the apparatus is an implicit connection generator for automatically extracting electrical connections between the circuit elements in the layout, the generator representing the connections by connectivity data stored in a design database contained within memory. Also within the apparatus is an explicit wiring generator for creating and preserving electrical connections between the circuit elements in response to user commands from the editor. The explicit wiring generator represents the connections by connectivity data stored in the design database.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: March 11, 1997
    Assignee: Mentor Graphics Corporation
    Inventors: Glenn Wikle, Suresh Ramaswamy, Thomas G. Matheson
  • Patent number: 5600567
    Abstract: A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16).
    Type: Grant
    Filed: November 3, 1994
    Date of Patent: February 4, 1997
    Assignee: Motorola, Inc.
    Inventors: Kayhan Kucukcakar, Rajesh Gupta, Thomas Tkacik
  • Patent number: 5586046
    Abstract: A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: December 17, 1996
    Assignee: Motorola, Inc.
    Inventors: David Feldbaumer, Frederick L. Lum, Vickie Mercier, Mark B. Weaver, Jan-Chung Wong, Rimon Shookhtim