Abstract: An improved semiconductor memory device in which an electric circuit operates normally is provided. A block of memory cells of a dynamic random access memory is provided on a semiconductor substrate. A dummy storage node is provided near a corner portion of the memory cell block. A dummy cell plate is provided such that it covers the dummy storage node and is electrically insulated from a main cell plate of the DRAM.
Type:
Grant
Filed:
June 21, 1996
Date of Patent:
May 5, 1998
Assignees:
Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
Abstract: The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit.
Abstract: A description is given of a switching device 1 comprising a transparent substrate 3, a switching film 5 of gadolinium having a thickness of 200 nm and a palladium layer (7) having a thickness of 10 nm. Under the influence of hydrogen gas, a transparent semiconductive layer (5) of GdH.sub.x (x>2) is formed which can be converted into a non-transparent layer of GdH.sub.x (x<2) by means of evacuation. The conversion between both compositions is reversible, and this phenomenon can for example be used in an optical switching element, a hydrogen sensor and thin displays.
Abstract: An epitaxial structure and method of manufacture for a single heterojunction bipolar transistor capable of being utilized in high-speed and high-power applications. Preferably, the epitaxial structure comprises an N-type collector made from InP, a P-type base made from InP, and an N-type emitter made from a semiconductor material of approximately 39 mole percent AlP and approximately 61 mole percent Sb.