Patents Examined by Aneta Cieslewicz
  • Patent number: 10141345
    Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display device. The array substrate of the present invention comprises: common electrodes, pixel electrodes, common electrode lines and at least one auxiliary common electrode line, and the at least one auxiliary common electrode line is arranged to intersect with and be electrically connected to the common electrode lines. The manufacturing method of an array substrate of the present invention comprises a step of forming common electrode lines and a step of forming auxiliary common electrode lines, wherein the auxiliary common electrode lines are arranged to intersect with and be electrically connected to the common electrode lines. The display device of the present invention comprises the above array substrate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 27, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jongwon Moon, Chuanyan Wang, Wenming Ren
  • Patent number: 10141201
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 10115920
    Abstract: An organic light emitting display device including a first electrode defined into red, green and blue sub-pixel regions; a hole injection layer disposed on the first electrode; a first hole transport layer disposed on the hole injection layer; first, second and third organic emission layers arranged on the first hole transport layer opposite to the respective red, green and blue sub-pixel regions; an electron transport layer disposed on the first, second and third organic emission layers; and a second electrode disposed on the electron transport layer. The second organic emission layer opposite to the green sub-pixel region is formed in a stacked structure including first and second hole host layers and a dopant host layer.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 30, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Kwang Hyun Kim
  • Patent number: 10096636
    Abstract: A light field imaging device includes an image sensor having a plurality of pixels arranged two-dimensionally therein; a microlens array formed over the image sensor, the microlens array having a plurality of microlenses arranged two-dimensionally therein; and a plurality of support structures formed between the image sensor and the microlens array for providing an air gap therebetween.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: October 9, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jong Eun Kim
  • Patent number: 10084050
    Abstract: A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10050228
    Abstract: Embodiments of the disclosure provide an Organic Light-Emitting Diode (OLED) display device and an encapsulation method thereof. The encapsulation method of the OLED display device comprises: providing a display substrate, the display substrate having a display region and a peripheral region provided outside the display region; forming a dam in the peripheral region of the display substrate; and forming a plurality of thin film encapsulation layers on the display substrate by using a single mask plate, wherein the plurality of thin film encapsulation layers envelop the dam therein.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 14, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Song Zhang
  • Patent number: 10032844
    Abstract: An organic light emitting display device and a method of manufacturing the same are provided that may reduce the resistance of a second electrode and may prevent corrosion and metal migration of a pad electrode without adding a separate mask process, or while reducing the number of mask processes. In the organic light emitting display device, an auxiliary line is connected to a second electrode through an auxiliary electrode, which is provided in the same layer as a first electrode, and a pad cover electrode is configured to cover an upper surface and a side surface of a pad connection electrode so as to prevent the pad connection electrode connected to a pad from being exposed outward.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 24, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Min-Joo Kim, Jung-Sun Beak, Jin-Hee Jang, Nam-Yong Kim
  • Patent number: 10020402
    Abstract: Provided are a thin film transistor (TFT) and a method of manufacturing the TFT. The TFT includes a substrate; a first conductive type semiconductor layer on the substrate and having a recess; second conductive type spacers at opposite side walls in the recess; a main semiconductor layer covering the first conductive type semiconductor layer and the second conductive type spacers and comprising a channel region and source and drain regions; a gate insulating layer on the main semiconductor layer; and a gate electrode on the gate insulating layer and corresponding to the recess.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 10, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Suk Hoon Ku, Hyunduck Cho
  • Patent number: 9997740
    Abstract: Discussed is a method for manufacturing an organic light emitting display device including forming a first electrode on a predetermined region of a substrate; forming an organic light emitting layer on the first electrode; forming a second electrode on the substrate including the organic light emitting layer; and bonding an encapsulation substrate to the substrate so as to electrically connect the encapsulation substrate and the second electrode to each other.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 12, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byung Chul Ahn, Bong geum Lee
  • Patent number: 9991285
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 9954132
    Abstract: A radiation detector is provided including a cathode, an anode, and a semiconductor wafer. The semiconductor wafer has opposed first and second surfaces. The cathode is mounted to the first surface, and the anode is mounted to the second surface. The semiconductor wafer is configured to be biased by a voltage between the cathode and the anode to generate an electrical field in the semiconductor wafer and to generate electrical signals responsive to absorbed radiation. The electrical field has an intensity having at least one local maximum disposed proximate to a corresponding at least one of the first surface or second surface.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 24, 2018
    Assignee: General Electric Company
    Inventors: Arie Shahar, Yaron Glazer, Jeffrey Levy, Avishai Ofan, Rotem Har-Lavan
  • Patent number: 9929217
    Abstract: A method of manufacturing an array substrate of a display is provided. The method includes forming a first bank material layer on a first substrate, wherein a material of the first bank material layer includes hydrophobic element; patterning the first bank material layer to form a first bank having at least one first concave; forming a first electrode on the first bank and in the first concave after the step of patterning the first bank material layer to form the first bank; and forming an color layer on the first electrode.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 27, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hong-Syu Chen, Wen-Pin Chen, Teng-Ke Chen, Tsu-Wei Chen, Kuo-Kuang Chen
  • Patent number: 9917117
    Abstract: A method of fabricating a display device including forming one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Moo Soon Ko
  • Patent number: 9865663
    Abstract: An organic light-emitting device including a substrate, first electrodes, first banks extending in a first direction, second banks extending in a second direction, organic functional layers each including an organic light-emitting layer, and a second electrode. The second banks include an organic fluorine compound, and have portions intersecting with and disposed above the first banks. Each of the first banks includes an organic bank layer including an organic material and an inorganic bank layer disposed on the organic bank layer. For each of the first banks, an uppermost surface thereof is a surface of the inorganic bank layer included therein.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 9, 2018
    Assignee: JOLED INC.
    Inventors: Nobuto Hosono, Kenichi Nendai
  • Patent number: 9865608
    Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 9, 2018
    Assignees: GLOBALFOUNDRIES Inc., Fraunhofer Gesellschaft zur Foerderung der angewandted Forschung e.V., NaMLab gGmbH
    Inventors: Johannes Mueller, Stefan Mueller, Stefan Flachowsky
  • Patent number: 9799606
    Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hoon Ahn, Sangho Rha, Jongmin Baek, Wookyung You, Nae-In Lee
  • Patent number: 9786229
    Abstract: Provided is a flexible display device including: a display region including pixels to display images, each pixel including an organic light emitting diode (OLED) configured to receive a signal from a signal line and power from a power line to display the images; a non-display region outside the display region where images are not to be displayed, the non-display region including: a circuit mount region including therein a driving circuit configured to supply the signal through the signal line and the power through the power line to each pixel; and a bending region formed between the display region and the circuit mount region and configured to be bent flexibly, wherein the signal line and the power line are formed on a same layer in the bending region.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: October 10, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: HoYoung Lee, ChangHeon Kang
  • Patent number: 9786693
    Abstract: A display panel is disclosed, which comprises: a first substrate; a scan line disposing on the first substrate; a data line disposing on the first substrate and overlapping with the scan line to form a first overlapping region; and an active layer disposing between the scan line and the data line and overlapping with the scan line and the data line to form a second overlapping region, wherein the second overlapping region locates in the first overlapping region and has a via, wherein an edge of the scan line has a first length along a substantial extension direction of the scan line in the first overlapping region, the active layer has a second length along a substantial extension direction of the scan line in the second overlapping region, and the second length is greater than the first length.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: October 10, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Ling Yu, Wei-Ching Cho, Hsia-Ching Chu
  • Patent number: 9702925
    Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 9666609
    Abstract: This disclosure relates to an array substrate wiring and manufacturing and repairing method thereof. The array substrate wiring comprises a first wiring formed on the substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer, being opposite to the first wiring, the second wiring being in a hanging state and not transmitting electric signals. By means of such a double layer wiring structure, the holes produced in the insulating layer are blocked using the second wiring in the upper layer, such that the outside moisture cannot reach the first wiring via the holes in the insulating layer, thereby protecting the first wiring for transmitting electric signals from corrosion and scratch.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 30, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chao Liu, Yujun Zhang, Zengsheng He, Lei Chen