Abstract: In one embodiment, a multiple interleaved coil structure for wireless power transfer includes a plurality of incomplete coils, each of the plurality of incomplete coils configured such that an alternating current flowing in the incomplete coil produces a magnetic field, and at least one interconnect between the plurality of incomplete coils, the at least one interconnect including a plurality of conductors arranged in such a way that the alternating current flowing in the plurality of conductors does not produce a magnetic field. Each of the plurality of incomplete coils includes a plurality of non-contiguous segments arranged in such a way that the incomplete coil will emit magnetic flux in response to an applied alternating current. The multiple interleaved coil structure can be implemented in a wireless power transmitter or a wireless power receiver.

Abstract: A method for detecting an islanding condition of a grid connected energy conversion system and related DC/AC converter apparatus to optimize performance in terms of preservation of the power quality, provide synchronized frequency perturbation for all the inverters of a plant, provide shut down capability within the time requested by utilities and safety standards and provide immunity to grid frequency fluctuations.

Abstract: A system for coupling a modulated voltage signal onto a current loop between a host device and a field device, in various embodiments, can include a circuit and an impedance bridge. The circuit is configured to flow current from the field device between two terminals of an input circuit in the host device, wherein the two terminals are included in the current loop. The impedance bridge is positioned between the two terminals and configured to modulate impedance to convert the current in a field loop produced by the field device into terminal voltage modulation, without introducing a DC voltage burden to the current.

Abstract: Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

Abstract: Disclosed is a reference voltage circuit with low temperature drift, including a first voltage unit, a second voltage unit and a K times' amplification unit. The first voltage unit is configured to generate a first voltage, with a first end thereof being grounded. The K times' amplification unit is configured to amplify the first voltage by K times, with a first end thereof being connected to a second end of the first voltage unit, and with a second end thereof being connected to a first end of the second voltage unit, wherein K is a constant greater than zero. The second voltage unit is configured to generate a second voltage, with the first end thereof being connected to a current source circuit, and a second end thereof being connected to a third end of the first voltage unit to serve as an output end of a reference voltage (VREF).

Abstract: A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.

Abstract: A half buffer circuit includes a current source coupled to a first node, a ground connection coupled to a second node, a feedback capacitor coupled between the first node and an output of the half buffer circuit, a transconductor element comprising a first input/output, a second input/output, and a transconductor element control input, and a switch network coupled between the first node and the second node. The first input/output is coupled to the output of the half buffer circuit. The second input/output is coupled to a ground connection. The switch network includes a first switch coupled between the first node and the second node, a second switch coupled between the first node and the transconductor element control input, and a third switch coupled between the second node and the transconductor element control input.

Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.

Abstract: Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

Abstract: Provided are a wireless power transmission device and a wireless power transmission system. The wireless power transmission device, according to one embodiment of the present invention, may comprise: a dipole coil comprising a core, and a conducting wire wound at the center part of the core; a power unit for supplying a current to the conducting wire; and a canceling coil for canceling a magnetic field radiated from a lateral surface of the dipole coil.

Abstract: A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not.

Abstract: A level shifting circuit for a voltage level translator includes first and second cross-coupled level shifters, each coupled between an output supply voltage and a lower rail and further coupled to receive first and second input control signals and to provide an output control signal. The second cross-coupled level shifter includes a first PMOS transistor coupled in series with a first NMOS transistor and a second PMOS transistor coupled in series with a second NMOS transistor. When an input supply voltage is less than a VCCI trigger associated with the output supply voltage, only the first and second NMOS transistors are coupled to contribute to the output control signal and when the input supply voltage is equal to or greater than the VCCI trigger, only the first and second PMOS transistors are coupled to contribute to the output control signal.

Abstract: An integrated circuit (2) has first and second domains (4). The first domain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.

Abstract: Methods and apparatus for an absorptive, phase invariant signal attenuator. In embodiments, PIN diodes can be coupled to a hybrid coupler. Incident power can be split by the coupler to a terminating resistor, a terminating diode, and a series diode. The terminating diode becomes increasingly well matched and absorptive over the attenuation range. The series diode becomes increasingly mismatched and reflective over the attenuation range. The terminating resistor increasingly absorbs incident power as the coupling value decreases due to increasing diode impedance over the attenuation range.

Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.

Abstract: A method for identifying correct operation of an electrical switching unit, having a full bridge circuit and inductive load operated by the full bridge circuit. The full bridge circuit includes a first semiconductor switching element supplying the inductive load with a first supply voltage potential and a second semiconductor switching element supplying the inductive load with a second supply voltage potential, having a smaller value than the first supply voltage potential. The first and second semiconductor switching element each have a diode.