Abstract: An electronic device comprises: an electronic component; a resin molded body in which the electronic component is embedded and fixed; and a bendable bend portion continuous with the resin molded body. For example, the bend portion is molded integrally with the resin molded body. Thus, electronic device can be reduced in size and thickness.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer and a tunnel barrier layer. The tunnel barrier layer has a main body region and a first interface region. The main body region has an oxide material of a first spinel structure represented by a general formula LM2O4. The first interface region has at least one element X selected from a group consisting of elements having a valence of 2 and elements having a valence of 3 excluding Al and has an oxide material of a second spinel structure represented by a general formula DG2O4(D represents one or more kinds of elements including Mg or the element X, and G represents one or more kinds of elements including Al or the element X). A content of the element X contained in the first interface region is larger than that of the element X contained in the main body region.

Abstract: Embodiments of the invention are directed to a method of forming a nanosheet transistor. A non-limiting example of the method includes forming a nanosheet stack having alternating layers of channel nanosheets and sacrificial nanosheets, wherein each of the layers of channel nanosheets includes a first type of semiconductor material, and wherein each of the layers of sacrificial nanosheets includes a second type of semiconductor material. The layers of sacrificial nanosheets are removed from the nanosheet stack, and layers of replacement sacrificial nanosheets are formed in the spaces that were occupied by the sacrificial nanosheets. Each of the layers of replacement sacrificial nanosheets includes a first type of non-semiconductor material.

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region and a pad region, a first conductive line on the cell array region and the pad region of the substrate, a second conductive line between the first conductive line and the substrate, the second conductive line including a first portion on the cell array region and a second portion on the pad region and exposed by the first conductive line in a plan view, a first edge pattern between the substrate and the first conductive line and between the first and second portions of the second conductive line, and a first cell contact plug on the pad region of the substrate that penetrates the first conductive line and the first edge pattern.

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: An organic EL device includes a pair of electrodes and an organic compound layer between pair of electrodes. The organic compound layer includes an emitting layer including a first material, a second material and a third material, in which singlet energy EgS(H) of the first material, singlet energy EgS(H2) of the second material, and singlet energy EgS(D) of the third material satisfy a specific relationship.

Abstract: Methods of making an integrated circuit for a single-molecule nucleic-acid assay platform. In one example, the method includes adhering a carbon nanotube to a surface of a transfer film, the transfer film comprising gold or a polymer; placing the surface of the transfer film on a CMOS integrated circuit; releasing the carbon nanotube from the transfer film; and forming a pair of post-processed electrodes proximate opposing ends of the carbon nanotube, the post-processed electrodes electrically connecting the carbon nanotube to the CMOS integrated circuit. The method can also include exposing the carbon nanotube to a diazonium salt solution to form a point defect on a portion of the carbon nanotube.

Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.

Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.

Abstract: A holding table for holding a wafer includes plural pins, and a wafer holding surface includes the tips of the plural pins. Therefore, small dust enters between the pins and thus is less readily left between the wafer holding surface and the wafer. Therefore, when the wafer is sucked and held, a gap is less readily made between the wafer holding surface and the wafer. Thus, the occurrence of the situation in which the wafer is held in a waving state is suppressed. For this reason, when a liquid resin is pushed to spread over the lower surface of the wafer, an air bubble enters less readily between the liquid resin and the wafer. This can suppress entry of the air bubble in a protective member obtained by curing the liquid resin.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: There is provided a technique that includes a first controller configured to acquire event data generated at a time of transferring a substrate and alarm data generated at a time of occurrence of a transfer error, a recorder configured to, while recording a transfer operation of the substrate as first image data, record the transfer operation of the substrate as second image data having a higher resolution than the first image data, a second controller configured to store the first image data in a first memory based on the event data, and store the second image data in a second memory based on the alarm data, and an operating controller configured to display at least the first image data and the second image data. The second controller displays both the first image data and the second image data on a same screen.

Abstract: There is provided an electro-optical device including a light-emitting layer that has a first light-emitting element and a second light-emitting element which are adjacent to each other and a color filter layer that has a first color filter provided corresponding to the first light-emitting element and a second color filter provided corresponding to the second light-emitting element, in which an inter-element distance between the first light-emitting element and the second light-emitting element is 1.5 ?m or less, and a thickness of layer between the light-emitting layer and the color filter layer is 6 times or less the inter-element distance.

Abstract: Integrated active-matrix light emitting pixel arrays based displays are provided. An example integrated device includes a backplane including pixel circuits conductively coupled to an array of light-emitting elements through intermediate conductive layers to form an array of active-matrix light-emitting pixels and a transparent conductive layer on the array of the light-emitting elements. Each of the light-emitting elements includes one or more quantum well semiconductor layers between a first contact electrode and a second contact electrode, and the first contact electrodes of the light-emitting elements is respectively bonded and conductively coupled to the pixel circuits in the backplane via the respective intermediate conductive layers.

Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.

Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.

Abstract: A foldable display panel is provided. The foldable display panel includes a foldable area and two non-foldable areas. The foldable display panel further includes at least two pixel units. Each of the pixel units includes three sub-pixels. A pattern of the sub-pixel in the foldable area is elliptical or is curved quadrilateral. A pattern of the sub-pixel in the non-foldable area is a rhombus. An ability of the sub-pixels located in the foldable area 100 to withstand stress during a bending process is enhanced. Detachment of an electroluminescent layer or a thin film encapsulation layer located in the foldable area is prevented, thereby a reliability of a display device is ensured and a quality of the product is improved.

Abstract: Provided herein may be a method of manufacturing a semiconductor device including the step of replacing sacrificial layers of a stack with line patterns through slits that pass through the stack and have different depths.