Abstract: An output circuit includes a first transistor coupled to an external terminal and having a gate terminal that receives a first drive signal. The first transistor pulls down a potential at the external terminal when activated in accordance with the first drive signal. The output circuit also includes a capacitor. The capacitor includes a first end coupled to the gate terminal of the first transistor. A clamp circuit, coupled to a second end of the capacitor, clamps the second end of the capacitor to a potential corresponding to the operation of the first transistor. The first transistor includes a drain terminal that is not coupled to the capacitor but is coupled to the external terminal.

Abstract: Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.