Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A system LSI comprises a signal generation circuit supplying 16 level set signals one by one to an internal power supply potential generation circuit to increase an internal power supply potential in 16 stages, a compare circuit comparing each internal power supply potential with a reference potential and outputting a signal of a level responsive to the result of comparison and a memory circuit temporarily storing the signal output from the compare circuit. Therefore, an optimum level set signal can be readily detected on the basis of an output signal from the memory circuit.