Abstract: A phase-locked loop (PLL) device is disclosed. The PLL device includes an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal, a timing error detector in communication with the interpolator for detecting a timing error value of the output signal, a loop filter in communication with the timing error detector for outputting the interpolation timing value to the interpolator in response to the timing error value, and a lock controller in communication with the loop filter for adjusting the interpolation timing value according to a timing quality of the output signal, and providing the adjusted interpolation timing value for the interpolator. A signal generation method for use in the data pick-up device with the aid of the digital phase-locked loop (PLL) device is also disclosed.

Abstract: A PLL device of a core logic chip includes a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals in response to a reference clock signal; a phase detector for generating an adjusting signal according to a phase difference between the reference clock signal and the output clock signals; and a control circuit for asserting a plurality of control signals to the controlled delay lines, respectively, according to the adjusting signal in order to have the delay times of the output clock signals independently adjusted and outputted again by the controlled delay lines. The delay times of the output clock signals can be determined according to a distribution table and further tuned according to a circuitry and a layout of the core logic chip.

Abstract: The present invention is a method and apparatus for providing a pseudo random sequence for a spread spectrum system that prevents interception and provides real estate and power consumption efficiency. A pseudo random sequence may be created in real-time by associating a pseudo random sequence of a channel location of the carrier frequency at an instant in time. For example, the entire band of the spread spectrum system may be scanned to detect a channel with a low received signal strength. The location of the channel, or the actual frequency of the channel, could be associated with a particular pseudo random sequence to create a hop set for frequency hopping. Additionally, the location of a characteristic of the spread spectrum system, such as a noise characteristic, could be utilized to determine a content of a pseudo random sequence.

Abstract: A method for calibrating an impulse radio distance measuring system comprising an impulse radio transceiver by conducting a pulse through a transmit receive switch to an antenna, receiving return energy which has been discharged across the transmit receive switch, determining a time of arrival of the return energy. The return energy is comprised of two distinct pulses, one of which represents discharge of the transmit switch as the original pulse travels to the antenna, the second represents energy reflected from the antenna and again discharged across the transmit receive switch while the switch is in the transmit position. The timing of the un-reflected energy is determined then the timing of the reflected energy relative to the un-reflected energy is determined through auto-correlation of the time domain scan of the received composite waveforms.

Abstract: Disclosed is a distortion compensation circuit that reduces the time for convergence of distortion compensation data, without impairing any stability of distortion compensation. The circuit includes an error computation and compensation data updating section that repeats a computation in which errors between an input orthogonal baseband transmission signal and a feedback signal obtained by demodulating part of the output from a power amplifier are computed to obtain error data and values obtained by multiplying this error data by step coefficients are added to distortion compensation data before updating, thereby computing distortion compensation data after updating. Distortion compensation data for compensation of nonlinear distortion is thus updated. Step coefficients are stored in a step coefficient data memory with respect to each of different input signal amplitude values.

Abstract: Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal's transitions.

Abstract: Combining signals includes receiving a plurality of groups of signals at a plurality of antennas at a mobile device, where each group of signals includes a plurality of signals, and each signal includes a time slot. The following is repeated for each group of signals of the plurality of groups of signals. An adjustment associated with a time slot of each signal is set. Each signal of the group of signals is adjusted at the time slot in accordance with the adjustment associated with the time slot. A signal quality associated with each time slot of each signal of the group of signals is established, and an optimal adjustment in accordance with the signal qualities is determined. The signals are adjusted in accordance with the optimal adjustment.

Abstract: A circuit is connected between a module and a pair of wires. The circuit includes a first connection line, a second connection line, radio frequency termination circuitry, a first transformer, a second transformer, a tapped inductance and a feedback cancellation filter. The first connection line is for connection to a first wire in the pair of wires. The second connection line is for connection to a second wire in the pair of wires. The radio frequency termination circuitry is connected between the first connection line and the second connection line. The first transformer has a first inductance and a second inductance. A first end of the first inductance is coupled to the first connection line. A first end of the second inductance is coupled to the second connection line. The second transformer includes a first inductance and a second inductance.

Abstract: A technique for identifying the encoding law utilized by a central office codec may be implemented in a receive modem. The encoding law, which is typically dictated by the country in which the central office is located, is employed to generate a plurality of transmission levels during an initialization period associated with the modem system. The receive modem analyzes a number of these transmission levels to determine whether the levels have certain characteristics associated with the particular encoding law followed by the central office codec. When the receive modem detects the codec type, it may transmit a suitable identifier back to the transmit modem.

Abstract: An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer further includes an input selector, which is coupled to toggle the input sample to at least a selected tap among the plurality of taps, responsive to a state of the equalizer, so that the equalizer operates in a first state as a feed forward equalizer, and in a second state as a blind equalizer.

Abstract: A delay locked loop of the present invention which synthesizes data and a clock inputted from outside has: voltage control delay loops having a plurality of delay circuit parts sequentially delaying the clock; a slot selector selecting a slot outputted from the delay circuit parts of the voltage control delay loops; a clock tree part creating a plurality of clocks with the same timing by an output of the slot selector; a phase control part phase-controlling the plurality of delay circuit parts corresponding to the output clock delay variation of the clock tree part; and sensing means on-off controlling all or part of the plurality of delay circuit parts and the slot selector.

Abstract: A method of signal equalization of a transmitted bit stream by means of a feed forward equalizer is provided, whereby the signal is decomposed into at least two components and the components are multiplied with equalization parameters to form equalized components, which are superposed to form an equalized signal, and whereby conditional bit error rates by counting faulty transmitted bits in dependence of preceding and succeeding bits are determined and the equalization parameters are tuned dependent on the determined conditional bit error rates.

Abstract: Briefly, a method and apparatus to compensate an imbalance of a modulator by providing calibration parameters to a calibration network. The modulator may receive a pair of predetermined sinusoidal in-phase and quadrature signals and output a distorted modulated signal. A processor may process spectral parameters at first and second harmonics of a detected envelope signal of the distorted modulated signal may generate the calibration parameters.

Abstract: A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.