Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.

Abstract: A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.

Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.

Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SKAM cell inverters may be asymmetrical in size. The memory may comp rise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

Abstract: The present invention proposes a lightning forecast method, comprising: identifying a Targeted Weather of SDA carrier (TWLC) based on radar reflectivity data; forecasting a future TWLC state based on the identified TWLC; building or updating an SDA model based on SDA observation data and detected TWLC state-related data; and calculating the probability of producing SDA in the forecasted future TWLC according to the SDA model.

Abstract: The present invention proposes a lightning forecast method, comprising: identifying a Targeted Weather of SDA carrier (TWLC) based on radar reflectivity data; forecasting a future TWLC state based on the identified TWLC; building or updating an SDA model based on SDA observation data and detected TWLC state-related data; and calculating the probability of producing SDA in the forecasted future TWLC according to the SDA model.

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract: A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.

Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.

Abstract: A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Abstract: A memory slot including a pad formed of a stack of regions made of thin layers, including a first region made of a nonmagnetic conducting material; a second region made of a magnetic material exhibiting a magnetization in a direction perpendicular to the principal plane of the pad; a third region made of a nonmagnetic conducting material of different characteristics to those of the first region; the pad resting on a conducting track adapted to cause the flow of a programming current of chosen sense, in which the pad has an asymmetric shape with respect to any plane perpendicular to the plane of the layers and parallel to the central axis of the track, and with respect to its barycenter.

Abstract: A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.