Abstract: A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to respective remote CPUs, that are connected to the local CPU in parallel with each other. Each remote CPU generates test patterns having undefined values assigned to pins of the logic circuit that do not participate in fault detection. The local CPU acquires pluralities of test patterns of the remote CPUs, generates new test patterns obtained by merging those test patterns that have identical pattern numbers among the pluralities of test patterns, and attempts to merge these newly generated test patterns.

Abstract: The invention is directed to techniques for providing a test procedure for testing a device using automatic test equipment (ATE). An ATE system includes memory having a test application stored therein, a test interface to connect to the device, and a processor coupled to the memory and the test interface. The processor is configured to operate in accordance with the test application to (i) provide a series of instructions based on a test procedure defining a device testing task, and (ii) control the test interface based on the provided series of instructions in order to test the device. The test procedure includes multiple test elements. Each test element defines instructions and programmable input variables that direct the processor to perform a particular test operation of the device testing task. The user of the ATE system combines test elements when creating the test procedure rather than write code from scratch, or modify code of prewritten templates.

Abstract: An on-the-fly algebraic error correction system and corresponding method for reducing error location search are presented. The method transforms an error locator polynomial into two transformed polynomials whose roots are elements in a smaller subfield, in order to significantly simplify the complexity, and to reduce the latency of the error correcting system hardware implementation. More specifically, if the error locator polynomial is over a finite field of (22n) elements, the transformed polynomial is over a finite subfield of (2n) elements. Thus, the problem of locating the roots of the error locator polynomial is reduced to locating the roots of the transformed polynomials. Assuming the error locator polynomial is of degree m, the present method requires at most (m2/2) evaluations of polynomials over the Galois field GF(22n) and (2n+1) evaluations over the subfield GF(2n) or root finding of two polynomials of at most a degree m over the subfield GF(2n).

Abstract: An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.

Abstract: A digital process monitor for measuring the performance of an integrated circuit has been developed. The digital process monitor includes: a ring oscillator that generates a series of clocked pulses, and a ripple counter that counts the clocked pulses. The count is measured for a prescribed period of time and the count corresponds to the performance of the integrated circuit.

Abstract: A receiving device in a multi-code mobile communication system is disclosed. In the multi-code mobile communication system, user serial data is broken down into a plurality of parallel data channels and parity data is generated from the user parallel data. The parity data is transmitted on a redundancy channel. In the receiving device, each symbol is decided using multi-codes from a signal received on the data and redundancy channels. An energy calculator in the receiving device calculates the energy of each decided symbol. A parity checker determines whether errors have been generated by checking the parity of symbol data, and a sign inverter inverts the sign of a symbol with the smallest energy as calculated by the energy calculator if it is determined that errors have been generated and thus corrects the errors.

Abstract: A fast error diagnosis system and process for combinational verification is described. The system and process localizes error sites in a combinational circuit implementation that has been shown to be inequivalent to its specification. In the typical case, it is not possible to identify the error location exactly. The invention uses a diagnosis strategy of gradually increasing the level of detail in the analysis algorithm to ultimately derive a small list of potential error sites in a short time. The invention combines the use of simulation, Binary Decision Diagrams, and Boolean satisfiability in a novel way to achieve the goal. The previous approaches have been limited in that they have either been constrained to a specific error model unlike the present invention, or they are inefficient in comparison to the present invention. The present invention allows for the final set of error sites derived to be small, where that set contains the actual error sites, and is derived in a reasonable amount of time.

Abstract: A communication subsystem (300) for transmitting error correction coded data in packets (200) includes an input buffer (302) storing unencoded data, a product coder (304) coupled to the input buffer, and a time division transmitter (306). The product coder (304) outputs product coded data packets (200) having a packet size, and the time division transmitter (306) transmits the product coded data packets (200) in a data section (109) of a frame (104). The data section (109) has a length substantially equal to an integer multiple of the packet size. The communication subsystem (300) may use a (s, t)×(n, m) product code specifically adapted to product code 53 byte ATM cells. A method for communicating error correction coded data in packets includes storing unencoded data in an input buffer (402), product coding the unencoded data (404), and outputting product coded data packets (406) having a packet size.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.

Abstract: A turbo coder block having a parallelization of degree n achieves increased processing speed. Each parallelized turbo coder block includes a first storage unit to store n samples of an input signal and a second storage unit to store n samples of at least one output signal of the parallelized turbo coding block. The parallelized turbo coder block further includes a bank of n delay units and is adapted to parallel process n samples of the input signal such that two delay units of the bank directly receive subsets of the n samples of the input signal, and an output signal of one delay unit is supplied to two delay units in the parallelized turbo coder block.

Abstract: A method of defective pixel address detection for an image sensor. The method comprises comparing a defective pixel address with a sensor address; outputting a defective pixel flag if the sensor address is equal to the defective pixel address; increasing an index by one; increasing the index by one if the sensor address is larger than the defective pixel address and the index value is not equal to zero, otherwise performing a following step; increasing the index by one if the sensor address is larger than the defective pixel address and the index value is equal to zero and a frame begins, otherwise performing a following step; comparing the defective pixel address with an empty signature; increasing the index by one if the defective pixel address is equal to the empty signature; and returning to the beginning step if the defective pixel address is not equal to the empty signature.

Abstract: When an error is detected in a received packet, a higher application is informed that the error occurred, and when no error is detected in the received packet, the higher application is informed that the packet has been received. If a next packet is received while a packet having the detected error is stored in a data storing region, an acknowledge signal indicating that the packet cannot be received is sent to a source node, and the packet having the detected error stored in the data storing region is invalidated by a request from the higher application. When the error is detected in a received packet, that packet stored in the data storing region is invalidated.

Abstract: A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal.

Abstract: A method of testing field programmable gate array (FPGA) resources and identifying faulty FPGA resources during normal on-line operation includes configuring an FPGA into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA throughout testing and identifying of the resources. Within the initial and subsequent self-testing areas, the FPGA resources are initially tested for faults. Upon detection of a fault in the FPGA resources, the initial self-testing area resources are reconfigured or subdivided and further tested in order to identify the faulty resource. Dependent upon the further test results, the FPGA resources may be further subdivided and tested until the faulty resource is identified. Once the faulty resource is identified, the FPGA is reconfigured to replace unusable faulty resources or to avoid faulty modes of operation of partially faulty resources diagnosed during further testing.

Abstract: A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.

Abstract: This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.

Abstract: An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.

Abstract: A quantization error correcting device corrects quantization error included in audio information at the time of decoding. The audio information is divided into a plurality of frequency bands and compressive-encoded for each frequency band with bit allocation determined based on audible frequency characteristic. The device includes: a detecting unit for detecting, based on bit allocation information indicating bit allocation and encoded values of the compressive-encoded audio information, a range of quantization error indicating a range in which audio information value before compressive-encoding corresponding to the encoded value exists; and an outputting unit for outputting a decoded value corresponding to one of the encoded values based on the detected range of quantization error and the ranges of quantization errors of other correlated ones of the encoded values.

Abstract: An iterative decoder for serially concatenated encoded data in which an outer code is a rate 1:2 repetition code operative to encode a data bit bn as two identical and interleaved coded bitsbcoded,n0,bcoded,n1. The decoder comprises a soft-input, soft-output inner decoder for which the input and output information are log likelihood ratios, input information being the log likelihood ratios of the encoded data and outer extrinsic information. Feedback outer extrinsic information is substracted from the inner decoder output information to produce inner extrinsic information. The log likelihood ratios Lno,Ln1, in the inner extrinsic information, corresponding to one information bit bn, are swapped to produce the feed back extrinsic information. The pairs of log likelihood ratios Ln0,Ln1 of the inner extrinsic information are summed to make a hard decision for the correspoding information bit.

Abstract: A circuit arrangement and method for minimizing bit errors, whereby respective corresponding bits of a bit sequence are compared to a corrected bit sequence or to an error signal and, given non-coincidence, the neighboring bits of the corrected bit sequence are utilized for correction of a decision criterion formed from the sampling time and a threshold.