Abstract: An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a code generator that supplies control routines to the microprocessor during at least part of the in-circuit programming operations. The code generator allows the in-circuit programming code to be updated in real time.

Abstract: An apparatus, system, and method are disclosed to shutdown a library manager while the library system remains in a partially online state. A message module is included to send a suspend message to a host such that the host stops sending library manager commands, a shutdown module is included to shutdown a library manager while a data storage device remains coupled to the host in an online state, a startup module is included to restart the library manager in response to a completed library manager maintenance operation, and a resume module is included to send a resume message to the host that the library manager is available for library manager commands.

Abstract: A data structure design system for prolonging the life of an FRAM (Ferroelectric Random Access Memory) includes a CPU (Central Processing Unit) (1), an FRAM (2), an SDRAM (Synchronous Dynamic Random Access Memory) (3), and a clock (4). The FRAM is divided into a plurality of fixed-size blocks, and is for storing data. The SDRAM is for storing data that need to be written to the FRAM, and includes three data structures: queue one, queue two, and hash table. The CPU is for reading data from external storages, storing the data in the SDRAM, reading data from the SDRAM, and writing the data to the FRAM via the three data structures. The clock is for recording a predetermined time used to determine the blocks in the FRAM in which data have not been read up to the predetermined time. A related data structure design method is also provided.

Abstract: An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

Abstract: One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.

Abstract: A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated in a cache bank having the lowest latency with respect to the given accessing processor. A currently accessed line in a different cache bank can be exchanged with a cache line in the cache bank with the lowest latency, and another line in the cache bank with lowest latency is moved to the different cache bank prior to the currently accessed line being moved to the cache bank with the lowest latency. Further replication of the cache line can be disabled when two or more processors alternately write to the cache line.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract: A point-to-point connected multiprocessing node uses a snooping-based cache-coherence filter to selectively direct relays of data request broadcasts. The filter includes shadow cache lines that are maintained to hold copies of the local cache lines of integrated circuits connected to the filter. The shadow cache lines are provided with additional entries so that if newly referenced data is added to a particular local cache line by “silently” removing an entry in the local cache line, the newly referenced data may be added to the shadow cache line without forcing the “blind” removal of an entry in the shadow cache line.