Abstract: An output circuit which suppresses the occurrence of leakage current from the power supply of an external element to the power supply of an internal device, even if the power supply voltage of the external element is higher than the power supply voltage of the internal device. Even if a voltage (5V) from an external circuit etc. which is higher than a power supply terminal 6 voltage (3V) is input to the output terminal 8, due to the fact that a floating state N-well B1 at the substrate of PMOS transistors P12, P13 and P14 rises to around 5V, PMOS transistor P12 and PMOS transistor P13 are put into an OFF state. If PMOS transistor P12 and PMOS transistor P13 are in the OFF state, the (5V) voltage is applied to PMOS transistor P1 and there is no flow of leakage current to the power supply terminal 6 through the substrate of PMOS transistor P1.

Abstract: A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.

Abstract: A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section delays a generated clock signal to output an internal clock signal, and a phase error-detecting section detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section to make the time difference substantially zero.

Abstract: Phase locked loops include a controlled oscillator that is responsive to a control signal, to generate an output signal, the frequency of which is a function of the control signal. A phase detector is responsive to a reference frequency input signal and to the output signal, to produce an error signal. A loop filter filters the error signal, to thereby produce the control signal. A bandpass filter is responsive to the error signal, to produce a filtered error signal at twice the frequency of the reference frequency, and an envelope detector is responsive to the filtered error signal to sense the amplitude of the filtered error signal. A variable attenuation circuit is responsive to the envelope detector output, to variably attenuate a phase locked loop input signal based on the amplitude of the filtered error signal, and thereby produce the reference frequency input signal.

Abstract: Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.

Abstract: A high precision charge pump used in a phase-lock loop incorporating a type-IV phase/frequency detector is designed and constructed to substantially eliminate the effects of ringing and glitch errors on the charge pump output current as averaged over a pump-up and pump-down cycle by the type-IV phase/frequency detector. The high precision charge pump is constructed exclusively of transistors of a single polarity (N-channels) that are so matched as to each have the same current characteristics. The current pulse length, absolute magnitude, and waveform envelopes of the charge pumps source and sink currents are defined by matched transistors. When the type-IV phase/frequency detector is operating in quasi flywheel mode, and no phase comparisons are being made, the charge pump's source current is equal to the sink current in all significant respects such that no incremental, residual charge is left on a loop capacitor following the conclusion of a sequential pump-up and pump-down sequence.

Abstract: The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branches to a first supply potential; a first capacitor connected between the output branches; two second resistors connected in series between the biasing branches; a second capacitor connected in series between the two second resistors; means for applying an input signal in the form of a differential current across the second capacitor; and means for supplying, as an output signal, the sum of the current in one of the first resistors and of a predetermined fraction of a corresponding component of the differential current constituting the input signal.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A method for improving the precision of a signal generator utilizing counters. The difference between an external standard signal frequency and an internal standard frequency is measured by digital counters. The signal of this internal standard frequency signal source is counted by a first counter and the frequency of an external standard frequency signal source is counted by a second counter. A calculating and control part determines the accurate frequency of internal standard frequency signal source from count values of both counters. The measurement frequency signal source generates a signal with the desired frequency. The circuit is digitally implemented.

Abstract: A clock driver circuit comprises a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common line 18 and 21. The second common line 21 is connected to a plurality of clock signal supply lines 20(1) through 20(m) which in turn are connected to the clock input nodes of second macro cells 16 each requiring a clock signal. In a test mode, the first and second common lines 18a and 21a of the first clock driver 15a and the first and second common lines 18b and 21b of the second clock driver 15b are electrically connected by first and second connection means 22 and 24, respectively. Thus, a clock driver circuit is provided that offers high driving ability with negligible clock skews in both normal mode and test mode.

Abstract: A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: The invention provides a PLL circuit which can form a phase difference between input and output signals with a high degree of accuracy without employing a current source for a very weak current and eliminates dependency of the phase difference upon the input signal frequency. In the PLL circuit, phase difference forming current is added within a term of a fixed period to a selected one of charge-up current and charge-down current, selected by a phase comparison circuit, of a charge pump circuit, which charges up or charges down a loop filter under the control of an output signal of a phase comparison circuit, to form a phase difference between input and output signals of the PLL circuit which are to be compared in phase by the phase comparison circuit. The magnitude of the phase difference depends upon and is controlled by a term within which the phase difference forming current.

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.