Abstract: Exemplary methods, apparatuses, and systems include a first layer of a virtual storage area network (VSAN) module receiving a write request from a data compute node. The write request includes data to be written and the VSAN module is distributed across a plurality of computers to provide an aggregate object store using storage attached to each of the plurality of computers. The first layer of the VSAN module calculates a checksum for the data to be written and passes the data to be written and the checksum to a second layer of the VSAN module. The second layer of the VSAN module calculates a first verification checksum for the data to be written. The data and the checksum are written to persistent storage in response to determining the first verification checksum matches the checksum passed by the first layer of the VSAN module.

Abstract: Techniques for interleaving information for media data are described. In at least some embodiments, interleaving information is propagated from a network-based service to endpoint devices that participate in communication sessions. The endpoint devices may utilize the interleaving information to interleave media data of communication sessions.

Abstract: Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.

Abstract: Exemplary methods, apparatuses, and systems maintain hole boundary information by calculating a block attribute parity value. For example, a request is received to write to a first block of a stripe of data. A block attribute of a second block is determined. The block attribute of the second block indicates whether the second block includes written data or is a hole. A block attribute parity value is calculated based upon both the block attribute of the first block and the block attribute of the second block. The block attribute of the first block indicates the first block includes written data based upon the received request. The block attribute parity value and the data parity value are stored on one of the physical storage devices in response to the received write request. As a result, if a disk is lost, holes can be recovered using the block attribute parity value.

Abstract: A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.

Abstract: An method of generating a featured scan pattern for test includes: providing a plurality of predetermined test patterns to perform test on a plurality of devices under test (DUT) under a stress condition to generate a plurality of test responses of each DUT; grouping a plurality of specific test responses of each DUT from the test responses of each DUT to determine a feature value corresponding to a failure feature for each DUT; and generating at least one featured test pattern according to the feature value of each DUT.

Abstract: The invention provides a semiconductor memory device capable of maintaining data reliability and shortening programming time. A flash memory of the invention includes a memory array 100, a page buffer/sensor circuit 160, an input/output buffer 110 connected to an external input/output terminal, and an ECC circuit 120 for checking and correcting data errors. In a programming operation, the input/output buffer 110 loads programming data into the page buffer/sensor circuit 160 and the ECC circuit 120 in parallel. The ECC circuit 120 writes parity bits generated from ECC calculation into a spare domain of the page buffer/sensor circuit 160. After the ECC procedure, the data held by the page buffer/sensor circuit 160 are programmed to a selected page.